)]}'
{
  "commit": "062f7a549024dca002cb9c8db878195ce93ea28b",
  "tree": "85198d90bf62b36c5570cadb3c248d003b1e01e1",
  "parents": [
    "2e284502288b705d1878a0aac29720b6d6e15fb8"
  ],
  "author": {
    "name": "Jan Beulich",
    "email": "jbeulich@suse.com",
    "time": "Fri Jun 13 08:40:32 2025 +0200"
  },
  "committer": {
    "name": "Jan Beulich",
    "email": "jbeulich@suse.com",
    "time": "Fri Jun 13 08:40:32 2025 +0200"
  },
  "message": "x86: refine UD\u003cn\u003e kind-of-insns\n\nWhile documentation of these continues to be lacking sufficient detail,\nit is becoming increasingly clear that in 66f1eba0b7e8 (\"x86: correct\nUDn\") I went too far with requiring operands, to populate a ModR/M byte.\nAMD hardware appears to always behave as indicated as \"may\" in PM 3.36,\nwhich for all practical purposes means there\u0027s no ModR/M byte. The SDM\n(rev 087) indicates that such behavior can occur on older hardware for\nUD0. Re-add an operand-less UD1 form (as well as its UD2B alias), while\nnewly adding such a form also for UD0. Because of the ambiguity, there\u0027s\nno good/easy way of handling both possibilities in the disassembler,\nwhich hence remains unaltered.\n\nFurther, from all information I\u0027m able to gather, the 0F opcode space\nwas only introduced with the i286; bump the minimal hardware requirement\nfor all UD\u003cn\u003e accordingly.\n",
  "tree_diff": [
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      "new_mode": 33188,
      "new_path": "gas/testsuite/gas/i386/arch-4.d"
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    },
    {
      "type": "modify",
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      "old_mode": 33188,
      "old_path": "opcodes/i386-opc.tbl",
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      "new_mode": 33188,
      "new_path": "opcodes/i386-opc.tbl"
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      "new_path": "opcodes/i386-tbl.h"
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}