)]}'
{
  "commit": "10ec3d5de0ee75ad56029bfa6b5d3be99f4eac3c",
  "tree": "021adface638a0d43f274066c8bfba23b5960520",
  "parents": [
    "280965fcedbc5e9b683d43cbb49c701071c1015b"
  ],
  "author": {
    "name": "Kito Cheng",
    "email": "kito.cheng@sifive.com",
    "time": "Tue Apr 29 11:40:15 2025 +0800"
  },
  "committer": {
    "name": "Nelson Chu",
    "email": "nelson@rivosinc.com",
    "time": "Wed Apr 30 08:04:38 2025 +0800"
  },
  "message": "RISC-V: Mark fgt.*/fge.* as instruction alias\n\nThey are instruction alias, but not mark correctly, and seems like we\ndon\u0027t have a good way to verify that since the disassembler doesn\u0027t\ndisassemble instruction into alias.\n\n[1] https://github.com/riscv-non-isa/riscv-asm-manual/pull/124\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "e07f72b89f2b2332f6e032147c1fb58353010767",
      "old_mode": 33188,
      "old_path": "opcodes/riscv-opc.c",
      "new_id": "6f49fdbaa7c321e5e455eea1eacbe102230eb0ec",
      "new_mode": 33188,
      "new_path": "opcodes/riscv-opc.c"
    }
  ]
}