)]}'
{
  "commit": "13aa307c9a9086d34b555cecf5f9388fa9b062f1",
  "tree": "4de500818ab17496162d8f65bb7c3d6ef42c7190",
  "parents": [
    "7c632c2a696fb68e5575db1e2c934788a831e578"
  ],
  "author": {
    "name": "Claudiu Zissulescu",
    "email": "claziss@synopsys.com",
    "time": "Fri Jul 07 12:58:34 2023 +0300"
  },
  "committer": {
    "name": "Claudiu Zissulescu",
    "email": "claziss@gmail.com",
    "time": "Fri Jul 07 13:08:04 2023 +0300"
  },
  "message": "arc: Update/Add ARCv3 support.\n\nThe ARC HS5x and ARC HS6x processors are based on the new ARCv3 ISA\nthat implements a full range of 32-bit and 64-bit instructions.  These\nprocessors feature a high-speed 10-stage, dual-issue pipeline that\noffers increased utilization of functional units with a limited\nincrease in power and area.  The HS5x processors feature a 32-bit\npipeline that can execute all ARCv3 32-bit instructions, while the\nHS6x processors feature a full 64-bit pipeline and register file that\ncan execute both 32-bit and 64-bit instructions.  In addition, the ARC\nHS6x supports 64-bit virtual and 52-bit physical address spaces to\nenable direct addressing of current and future large memories, as well\nas 128-bit loads and stores for efficient data movement.\n\nThis readelf patch updates/adds Synopsys ARCv3 machine name fileds and\nsupported relocations.\n\nSigned-off-by: Claudiu Zissulescu \u003cclaziss@synopsys.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "97d72d0b95f02846f51b06e284e70178803215e2",
      "old_mode": 33188,
      "old_path": "binutils/readelf.c",
      "new_id": "bb488ef2a5e68e5c07b40d8c2bb3486638f5f98c",
      "new_mode": 33188,
      "new_path": "binutils/readelf.c"
    }
  ]
}