)]}'
{
  "commit": "15db2284f2f8259e46635ca6df3efc772d951fac",
  "tree": "9942e0188fa23d186cca444c0520fbf3d6522bb9",
  "parents": [
    "3c83779e12feb56fd20a30eeafcf4b2bea571818"
  ],
  "author": {
    "name": "Simon Marchi",
    "email": "simon.marchi@efficios.com",
    "time": "Fri Sep 08 11:20:58 2023 -0400"
  },
  "committer": {
    "name": "Simon Marchi",
    "email": "simon.marchi@efficios.com",
    "time": "Fri Sep 08 13:14:41 2023 -0400"
  },
  "message": "gdb/doc: describe x87 registers\n\nWhile investigating this [1], I initially had no idea what register\n\"fioff\" stood for, making it difficult to map it to something in the\nIntel or AMD manuals.  Similarly, I can imaging someone familiar with\nx87 to want to print the \"x87 last instruction address\", and have no\nclue that GDB makes it available as register \"fioff\".  The names of the\nx87 state fields don\u0027t seem to be standardized, they even change between\nsections of the Intel manual (between the FSAVE, FXSAVE and XSAVE area\ndescriptions).\n\nAdd some details to the doc to help one map GDB register names to x87\nstate fields.\n\n[1] https://inbox.sourceware.org/gdb-patches/20230908022722.430741-1-simon.marchi@efficios.com/T/#u\n\nChange-Id: I0ea1eb648358e62da4aa87eea3515ee8a09f2762\nApproved-By: Eli Zaretskii \u003celiz@gnu.org\u003e\nApproved-By: Pedro Alves \u003cpedro@palves.net\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "72083fc5b64f490502c73a8e604efb6a95ad1694",
      "old_mode": 33188,
      "old_path": "gdb/doc/gdb.texinfo",
      "new_id": "9b7e06f315665207ad32dbfeeb1d67148c7c2491",
      "new_mode": 33188,
      "new_path": "gdb/doc/gdb.texinfo"
    }
  ]
}