)]}'
{
  "commit": "1c87a0ffc299a5e74f43b6cbee3e81769516d30f",
  "tree": "3dfd8bcf2c481332aca6ff88699b82b3b830dbd0",
  "parents": [
    "ef8bee09ef09230e4247ea962698bf5a0b4892cc"
  ],
  "author": {
    "name": "Alice Carlotti",
    "email": "alice.carlotti@arm.com",
    "time": "Fri Apr 04 19:23:11 2025 +0100"
  },
  "committer": {
    "name": "Alice Carlotti",
    "email": "alice.carlotti@arm.com",
    "time": "Tue May 13 17:57:30 2025 +0100"
  },
  "message": "aarch64: Replace incorrect comment\n\nThe comment explaining the placement of the cfinv entry before the\ngeneric msr entry in the opcode table was incorrect.  The issue is\nunrelated to the all ones bitmask for cfinv, and is actually due the\nlarge number of architectural aliases of the msr instruction.\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "77c3dc855b739a1e283d2945a9f1a73d7b18e4c1",
      "old_mode": 33188,
      "old_path": "opcodes/aarch64-tbl.h",
      "new_id": "f43e1e32b80f2551573983d46946065d1d0bdde6",
      "new_mode": 33188,
      "new_path": "opcodes/aarch64-tbl.h"
    }
  ]
}