)]}'
{
  "commit": "1fa0873f1d99fc24de0ccc3de486ab8ad4ce966a",
  "tree": "b63380850d38abddd07f98ed0889a38e2ab15fcb",
  "parents": [
    "64273f18ecf2436eae3fe0d4a3db22d2ca66b32b"
  ],
  "author": {
    "name": "Haochen Jiang",
    "email": "haochen.jiang@intel.com",
    "time": "Thu Jan 02 10:14:37 2025 +0800"
  },
  "committer": {
    "name": "Haochen Jiang",
    "email": "haochen.jiang@intel.com",
    "time": "Thu Jan 02 10:14:37 2025 +0800"
  },
  "message": "Support Intel AMX-TRANSPOSE\n\nIn this patch, we will support AMX-TRANSPOSE. Since AMX-TRANSPOSE\nwill be used with other CPUIDs very often, we put it into\nCPU_FLAGS_COMMON.\n\nTo implement TMM pair, we reused ImplicitGroup and adjust the condition\nin process_operands for the instructions.\n\nAPX_F extension is also handled in this patch, where it extends\nT2RPNTLVW[Z0,Z1][,T1] to EVEX.128.NP/66.0F38.W0 6E/6F !(11):rrr:100\nwith NF\u003d0.\n\nAlso, TTDPFP16PS should base on AMX_FP16, not AMX_BF16 in ISE055.\nIt would be fixed in ISE056.\n\ngas/ChangeLog:\n\n\t* config/tc-i386.c (cpu_arch): Add amx_transpose.\n\t(_is_cpu): Ditto.\n\t(process_operands): Adjust the condition for AMX-TRANSPOSE.\n\t* doc/c-i386.texi: Document .amx_transpose.\n\t* testsuite/gas/i386/x86-64.exp: Run AMX-TRANSPOSE tests.\n\t* testsuite/gas/i386/x86-64-amx-transpose-bad.d: New test.\n\t* testsuite/gas/i386/x86-64-amx-transpose-bad.s: Ditto.\n\t* testsuite/gas/i386/x86-64-amx-transpose-intel.d: Ditto.\n\t* testsuite/gas/i386/x86-64-amx-transpose-inval.l: Ditto.\n\t* testsuite/gas/i386/x86-64-amx-transpose-inval.s: Ditto.\n\t* testsuite/gas/i386/x86-64-amx-transpose.d: Ditto.\n\t* testsuite/gas/i386/x86-64-amx-transpose.s: Ditto.\n\nopcodes/ChangeLog:\n\n\t* i386-dis.c (MOD_VEX_0F386E_X86_64_W_0): New.\n\t(MOD_VEX_0F386F_X86_64_W_0): Ditto.\n\t(PREFIX_VEX_0F385F_X86_64_W_0_L_0): Ditto.\n\t(PREFIX_VEX_0F386B_X86_64_W_0_L_0): Ditto.\n\t(PREFIX_VEX_0F386E_X86_64_W_0_M_0_L_0): Ditto.\n\t(PREFIX_VEX_0F386F_X86_64_W_0_M_0_L_0): Ditto.\n\t(X86_64_VEX_0F385F): Ditto.\n\t(X86_64_VEX_0F386B): Ditto.\n\t(X86_64_VEX_0F386E): Ditto.\n\t(X86_64_VEX_0F386F): Ditto.\n\t(VEX_LEN_0F385F_X86_64_W_0): Ditto.\n\t(VEX_LEN_0F386B_X86_64_W_0): Ditto.\n\t(VEX_LEN_0F386E_X86_64_W_0_M_0): Ditto.\n\t(VEX_LEN_0F386F_X86_64_W_0_M_0): Ditto.\n\t(VEX_W_0F385F_X86_64): Ditto.\n\t(VEX_W_0F386B_X86_64): Ditto.\n\t(VEX_W_0F386E_X86_64): Ditto.\n\t(VEX_W_0F386F_X86_64): Ditto.\n\t(mod_table): Add MOD_VEX_0F386E_X86_64_W_0,\n\tMOD_VEX_0F386F_X86_64_W_0.\n\t(prefix_table): Add PREFIX_VEX_0F386E_X86_64_W_0_M_0_L_0,\n\tPREFIX_VEX_0F386F_X86_64_W_0_M_0_L_0.\n\tAdd new instructions for PREFIX_VEX_0F386C_X86_64_W_0_L_0.\n\t(x86_64_table): Add X86_64_VEX_0F385F, X86_64_VEX_0F386B,\n\tX86_64_VEX_0F386E, X86_64_VEX_0F386F.\n\t(vex_len_table): Add VEX_LEN_0F385F_X86_64_W_0,\n\tVEX_LEN_0F386B_X86_64_W_0, VEX_LEN_0F386E_X86_64_W_0_M_0,\n\tVEX_LEN_0F386F_X86_64_W_0_M_0.\n\t(vex_w_table): Add VEX_W_0F385F_X86_64, VEX_W_0F386B_X86_64,\n\tVEX_W_0F386E_X86_64, VEX_W_0F386F_X86_64.\n\t* i386-gen.c (cpu_flag_init): Add AMX_TRANSPOSE.\n\t(cpu_flags): Add CpuAMX_TRANSPOSE.\n\t* i386-init.h: Regenerated.\n\t* i386-mnem.h: Ditto.\n\t* i386-opc.h (CpuAMX_TRANSPOSE): New.\n\t(i386_cpu): Add cpuamx_transpose.\n\t* i386-opc.tbl: Add AMX-TRANSPOSE instructions.\n\t* i386-tbl.h: Regenerated.\n\nCo-authored-by: Hu, Lin1 \u003clin1.hu@intel.com\u003e\n",
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