)]}'
{
  "commit": "21629cf8bc2b16d3c75dff0c3f1222b714bf90c2",
  "tree": "9e0d8099afb0614bd53bb12aa10e704c200204ec",
  "parents": [
    "b1458c4569ec9eeb077e928b0eb6b210c7eb647f"
  ],
  "author": {
    "name": "Maciej W. Rozycki",
    "email": "macro@orcam.me.uk",
    "time": "Sat May 29 03:26:32 2021 +0200"
  },
  "committer": {
    "name": "Maciej W. Rozycki",
    "email": "macro@orcam.me.uk",
    "time": "Sat May 29 03:26:32 2021 +0200"
  },
  "message": "MIPS/opcodes: Properly handle ISA exclusion\n\nRemove the hack used for MIPSr6 ISA exclusion from `cpu_is_member\u0027 and\nhandle the exclusion for any ISA levels properly in `opcode_is_member\u0027.\nFlatten the structure of the `if\u0027 statements there.  No functional\nchange for the existing opcode tables.\n\n\tinclude/\n\t* opcode/mips.h (cpu_is_member): Remove code for MIPSr6 ISA\n\texclusion.\n\t(opcode_is_member): Handle ISA level exclusion.\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "b51782f5093372922391a12114d340c4f1e46877",
      "old_mode": 33188,
      "old_path": "include/ChangeLog",
      "new_id": "d1a0485fb12d17b4041dcdb84d0321bea6c947a5",
      "new_mode": 33188,
      "new_path": "include/ChangeLog"
    },
    {
      "type": "modify",
      "old_id": "aa6e9d7cee988ae8b99e568be340c5b03ccff0d8",
      "old_mode": 33188,
      "old_path": "include/opcode/mips.h",
      "new_id": "9add3c9d5bf5b99921ca95da2cfcaad895207992",
      "new_mode": 33188,
      "new_path": "include/opcode/mips.h"
    }
  ]
}