)]}'
{
  "commit": "25236d63fdb138e24cb34aa6c513ae8de2dac7b8",
  "tree": "a22052af6988dd1f70eb08d863e9892f093df565",
  "parents": [
    "27cfd142d0a7e378d19aa9a1278e2137f849b71b"
  ],
  "author": {
    "name": "Christoph Müllner",
    "email": "christoph.muellner@vrull.eu",
    "time": "Thu Jul 21 00:26:29 2022 +0200"
  },
  "committer": {
    "name": "Philipp Tomsich",
    "email": "philipp.tomsich@vrull.eu",
    "time": "Thu Sep 22 18:06:09 2022 +0200"
  },
  "message": "RISC-V: Add support for literal instruction arguments\n\nThis patch introduces support for arbitrary literal instruction\narguments, that are not encoded in the opcode.\n\nA typical use case for this feature would be an instruction that\napplies an implicit shift by a constant value on an immediate\n(that is a real operand). With this patch it is possible to make\nthis shift visible in the dissasembly and support such artificial\nparameter as part of the asssembly code.\n\nCo-developed-by: Lifang Xia \u003clifang_xia@linux.alibaba.com\u003e\nSigned-off-by: Christoph Müllner \u003cchristoph.muellner@vrull.eu\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "00e4635de6e0bce6a03514294bed5c86d2f82a17",
      "old_mode": 33188,
      "old_path": "gas/config/tc-riscv.c",
      "new_id": "d9f63b1139859ba8332377e68c87446484af92bc",
      "new_mode": 33188,
      "new_path": "gas/config/tc-riscv.c"
    },
    {
      "type": "modify",
      "old_id": "2594e8182544832499de0cb338adb70793c628a8",
      "old_mode": 33188,
      "old_path": "opcodes/riscv-dis.c",
      "new_id": "f2d399260c1854d653f406e78e6fd79d42434985",
      "new_mode": 33188,
      "new_path": "opcodes/riscv-dis.c"
    }
  ]
}