| //Original:/testcases/core/c_dsp32alu_rh_p/c_dsp32alu_rh_p.dsp | |
| // Spec Reference: dsp32alu dreg (half) | |
| # mach: bfin | |
| .include "testutils.inc" | |
| start | |
| imm32 r0, 0x34678911; | |
| imm32 r1, 0x2789ab1d; | |
| imm32 r2, 0x34645515; | |
| imm32 r3, 0x46667717; | |
| imm32 r4, 0xd678891b; | |
| imm32 r5, 0x6e89ab1d; | |
| imm32 r6, 0x74b45515; | |
| imm32 r7, 0x866cc777; | |
| R0.H = R0.L + R0.L (NS); | |
| R1.H = R0.L + R1.H (NS); | |
| R2.H = R0.H + R2.L (NS); | |
| R3.H = R0.H + R3.H (NS); | |
| R4.H = R0.L + R4.L (NS); | |
| R5.H = R0.L + R5.H (NS); | |
| R6.H = R0.H + R6.L (NS); | |
| R7.H = R0.H + R7.H (NS); | |
| CHECKREG r4, 0x122C891B; | |
| CHECKREG r5, 0xF79AAB1D; | |
| CHECKREG r6, 0x67375515; | |
| CHECKREG r7, 0x988EC777; | |
| CHECKREG r4, 0x122C891B; | |
| CHECKREG r5, 0xF79AAB1D; | |
| CHECKREG r6, 0x67375515; | |
| CHECKREG r7, 0x988EC777; | |
| imm32 r0, 0x12348911; | |
| imm32 r1, 0x2e89ab1d; | |
| imm32 r2, 0x34f45515; | |
| imm32 r3, 0x46d67717; | |
| imm32 r4, 0x567b891b; | |
| imm32 r5, 0x6789ab1d; | |
| imm32 r6, 0x7444b515; | |
| imm32 r7, 0x86667a77; | |
| R0.H = R1.L + R0.L (NS); | |
| R1.H = R1.L + R1.H (NS); | |
| R2.H = R1.H + R2.L (NS); | |
| R3.H = R1.H + R3.H (NS); | |
| R4.H = R1.L + R4.L (NS); | |
| R5.H = R1.L + R5.H (NS); | |
| R6.H = R1.H + R6.L (NS); | |
| R7.H = R1.H + R7.H (NS); | |
| CHECKREG r4, 0x3438891B; | |
| CHECKREG r5, 0x12A6AB1D; | |
| CHECKREG r6, 0x8EBBB515; | |
| CHECKREG r7, 0x600C7A77; | |
| CHECKREG r4, 0x3438891B; | |
| CHECKREG r5, 0x12A6AB1D; | |
| CHECKREG r6, 0x8EBBB515; | |
| CHECKREG r7, 0x600C7A77; | |
| imm32 r0, 0x85678911; | |
| imm32 r1, 0x3989ab1d; | |
| imm32 r2, 0x34445515; | |
| imm32 r3, 0x46a67717; | |
| imm32 r4, 0x5e78891b; | |
| imm32 r5, 0x67d9ab1d; | |
| imm32 r6, 0x744b5515; | |
| imm32 r7, 0x86668777; | |
| R0.H = R2.L + R0.L (NS); | |
| R1.H = R2.L + R1.H (NS); | |
| R2.H = R2.H + R2.L (NS); | |
| R3.H = R2.H + R3.H (NS); | |
| R4.H = R2.L + R4.L (NS); | |
| R5.H = R2.L + R5.H (NS); | |
| R6.H = R2.H + R6.L (NS); | |
| R7.L = R2.H + R7.H (NS); | |
| CHECKREG r4, 0xDE30891B; | |
| CHECKREG r5, 0xBCEEAB1D; | |
| CHECKREG r6, 0xDE6E5515; | |
| CHECKREG r7, 0x86660FBF; | |
| CHECKREG r4, 0xDE30891B; | |
| CHECKREG r5, 0xBCEEAB1D; | |
| CHECKREG r6, 0xDE6E5515; | |
| CHECKREG r7, 0x86660FBF; | |
| imm32 r0, 0x25678911; | |
| imm32 r1, 0x2789ab1d; | |
| imm32 r2, 0x3e445515; | |
| imm32 r3, 0x46d67717; | |
| imm32 r4, 0x567f891b; | |
| imm32 r5, 0x6789bb1d; | |
| imm32 r6, 0x74445515; | |
| imm32 r7, 0x86667b77; | |
| R0.H = R3.L + R0.L (NS); | |
| R1.H = R3.L + R1.H (NS); | |
| R2.H = R3.H + R2.L (NS); | |
| R3.H = R3.H + R3.H (NS); | |
| R4.H = R3.L + R4.L (NS); | |
| R5.H = R3.L + R5.H (NS); | |
| R6.H = R3.H + R6.L (NS); | |
| R7.H = R3.H + R7.H (NS); | |
| CHECKREG r4, 0x0032891B; | |
| CHECKREG r5, 0xDEA0BB1D; | |
| CHECKREG r6, 0xE2C15515; | |
| CHECKREG r7, 0x14127B77; | |
| CHECKREG r4, 0x0032891B; | |
| CHECKREG r5, 0xDEA0BB1D; | |
| CHECKREG r6, 0xE2C15515; | |
| CHECKREG r7, 0x14127B77; | |
| imm32 r0, 0x15678911; | |
| imm32 r1, 0x2789ab1d; | |
| imm32 r2, 0x34445515; | |
| imm32 r3, 0x46667717; | |
| imm32 r4, 0x5678891b; | |
| imm32 r5, 0x6789ab1d; | |
| imm32 r6, 0x74445515; | |
| imm32 r7, 0x86667777; | |
| R0.H = R4.L + R0.L (NS); | |
| R1.H = R4.L + R1.H (NS); | |
| R2.H = R4.H + R2.L (NS); | |
| R3.H = R4.H + R3.H (NS); | |
| R4.H = R4.L + R4.L (NS); | |
| R5.H = R4.L + R5.H (NS); | |
| R6.H = R4.H + R6.L (NS); | |
| R7.H = R4.H + R7.H (NS); | |
| CHECKREG r4, 0x1236891B; | |
| CHECKREG r5, 0xF0A4AB1D; | |
| CHECKREG r6, 0x674B5515; | |
| CHECKREG r7, 0x989C7777; | |
| CHECKREG r4, 0x1236891B; | |
| CHECKREG r5, 0xF0A4AB1D; | |
| CHECKREG r6, 0x674B5515; | |
| CHECKREG r7, 0x989C7777; | |
| imm32 r0, 0xa5678911; | |
| imm32 r1, 0x2a89ab1d; | |
| imm32 r2, 0x34d45515; | |
| imm32 r3, 0x466b7717; | |
| imm32 r4, 0x5678f91b; | |
| imm32 r5, 0x6789ab1d; | |
| imm32 r6, 0x7444a515; | |
| imm32 r7, 0x86667b77; | |
| R0.H = R5.L + R0.L (NS); | |
| R1.H = R5.L + R1.H (NS); | |
| R2.H = R5.H + R2.L (NS); | |
| R3.H = R5.H + R3.H (NS); | |
| R4.H = R5.L + R4.L (NS); | |
| R5.H = R5.L + R5.H (NS); | |
| R6.H = R5.H + R6.L (NS); | |
| R7.H = R5.H + R7.H (NS); | |
| CHECKREG r4, 0xA438F91B; | |
| CHECKREG r5, 0x12A6AB1D; | |
| CHECKREG r6, 0xB7BBA515; | |
| CHECKREG r7, 0x990C7B77; | |
| CHECKREG r4, 0xA438F91B; | |
| CHECKREG r5, 0x12A6AB1D; | |
| CHECKREG r6, 0xB7BBA515; | |
| CHECKREG r7, 0x990C7B77; | |
| imm32 r0, 0xf5678911; | |
| imm32 r1, 0x2f89ab1d; | |
| imm32 r2, 0x34445515; | |
| imm32 r3, 0x46f67717; | |
| imm32 r4, 0x5678891b; | |
| imm32 r5, 0x678fab1d; | |
| imm32 r6, 0x7444f515; | |
| imm32 r7, 0x86667f77; | |
| R0.L = R6.L + R0.L (NS); | |
| R1.H = R6.L + R1.H (NS); | |
| R2.H = R6.H + R2.L (NS); | |
| R3.H = R6.H + R3.H (NS); | |
| R4.H = R6.L + R4.L (NS); | |
| R5.H = R6.L + R5.H (NS); | |
| R6.H = R6.H + R6.L (NS); | |
| R7.H = R6.H + R7.H (NS); | |
| CHECKREG r4, 0x7E30891B; | |
| CHECKREG r5, 0x5CA4AB1D; | |
| CHECKREG r6, 0x6959F515; | |
| CHECKREG r7, 0xEFBF7F77; | |
| CHECKREG r4, 0x7E30891B; | |
| CHECKREG r5, 0x5CA4AB1D; | |
| CHECKREG r6, 0x6959F515; | |
| CHECKREG r7, 0xEFBF7F77; | |
| imm32 r0, 0x15678911; | |
| imm32 r1, 0x2789ab1d; | |
| imm32 r2, 0x34445515; | |
| imm32 r3, 0x46667717; | |
| imm32 r4, 0x5678891b; | |
| imm32 r5, 0x6789ab1d; | |
| imm32 r6, 0x74445515; | |
| imm32 r7, 0x86667777; | |
| R0.H = R7.L + R0.L (NS); | |
| R1.H = R7.L + R1.H (NS); | |
| R2.H = R7.H + R2.L (NS); | |
| R3.H = R7.H + R3.H (NS); | |
| R4.H = R7.L + R4.L (NS); | |
| R5.H = R7.L + R5.H (NS); | |
| R6.H = R7.H + R6.L (NS); | |
| R7.H = R7.H + R7.H (NS); | |
| CHECKREG r4, 0x0092891B; | |
| CHECKREG r5, 0xDF00AB1D; | |
| CHECKREG r6, 0xDB7B5515; | |
| CHECKREG r7, 0x0CCC7777; | |
| CHECKREG r4, 0x0092891B; | |
| CHECKREG r5, 0xDF00AB1D; | |
| CHECKREG r6, 0xDB7B5515; | |
| CHECKREG r7, 0x0CCC7777; | |
| imm32 r0, 0x56678911; | |
| imm32 r1, 0x2789ab1d; | |
| imm32 r2, 0x34645515; | |
| imm32 r3, 0x466a7717; | |
| imm32 r4, 0x5678e91b; | |
| imm32 r5, 0x6789af1d; | |
| imm32 r6, 0x744455f5; | |
| imm32 r7, 0x866677b7; | |
| R6.H = R2.L + R3.L (S); | |
| R1.H = R4.L + R5.H (S); | |
| R5.H = R7.H + R2.L (S); | |
| R3.H = R0.H + R0.H (S); | |
| R0.H = R3.L + R4.L (S); | |
| R2.H = R5.L + R7.H (S); | |
| R7.H = R6.H + R7.L (S); | |
| R4.H = R1.H + R6.H (S); | |
| CHECKREG r4, 0x7FFFE91B; | |
| CHECKREG r5, 0xDB7BAF1D; | |
| CHECKREG r6, 0x7FFF55F5; | |
| CHECKREG r7, 0x7FFF77B7; | |
| CHECKREG r4, 0x7FFFE91B; | |
| CHECKREG r5, 0xDB7BAF1D; | |
| CHECKREG r6, 0x7FFF55F5; | |
| CHECKREG r7, 0x7FFF77B7; | |
| imm32 r0, 0x95678911; | |
| imm32 r1, 0x2989ab1d; | |
| imm32 r2, 0x34445515; | |
| imm32 r3, 0x46967717; | |
| imm32 r4, 0x5679891b; | |
| imm32 r5, 0x6789ab1d; | |
| imm32 r6, 0x74449515; | |
| imm32 r7, 0x86667977; | |
| R3.H = R4.L + R0.L (S); | |
| R1.H = R6.L + R3.H (S); | |
| R4.H = R3.H + R2.L (S); | |
| R6.H = R7.H + R1.H (S); | |
| R2.H = R5.L + R4.L (S); | |
| R7.H = R2.L + R7.H (S); | |
| R0.H = R1.H + R6.L (S); | |
| R5.H = R0.H + R5.H (S); | |
| CHECKREG r4, 0xD515891B; | |
| CHECKREG r5, 0xE789AB1D; | |
| CHECKREG r6, 0x80009515; | |
| CHECKREG r7, 0xDB7B7977; | |
| CHECKREG r4, 0xD515891B; | |
| CHECKREG r5, 0xE789AB1D; | |
| CHECKREG r6, 0x80009515; | |
| CHECKREG r7, 0xDB7B7977; | |
| pass |