blob: e7a32b04ce7e16b34101cbe0346176d04fa9bc27 [file] [log] [blame]
# frv testcase for fblglr $FCCi,$hint
# mach: all
.include "testutils.inc"
start
.global fblglr
fblglr:
set_spr_addr bad,lr
set_fcc 0x0 0
fblglr fcc0,0
set_spr_addr bad,lr
set_fcc 0x1 1
fblglr fcc1,1
set_spr_addr ok3,lr
set_fcc 0x2 2
fblglr fcc2,2
fail
ok3:
set_spr_addr ok4,lr
set_fcc 0x3 3
fblglr fcc3,3
fail
ok4:
set_spr_addr ok5,lr
set_fcc 0x4 0
fblglr fcc0,0
fail
ok5:
set_spr_addr ok6,lr
set_fcc 0x5 1
fblglr fcc1,1
fail
ok6:
set_spr_addr ok7,lr
set_fcc 0x6 2
fblglr fcc2,2
fail
ok7:
set_spr_addr ok8,lr
set_fcc 0x7 3
fblglr fcc3,3
fail
ok8:
set_spr_addr bad,lr
set_fcc 0x8 0
fblglr fcc0,0
set_spr_addr bad,lr
set_fcc 0x9 1
fblglr fcc1,1
set_spr_addr okb,lr
set_fcc 0xa 2
fblglr fcc2,2
fail
okb:
set_spr_addr okc,lr
set_fcc 0xb 3
fblglr fcc3,3
fail
okc:
set_spr_addr okd,lr
set_fcc 0xc 0
fblglr fcc0,0
fail
okd:
set_spr_addr oke,lr
set_fcc 0xd 1
fblglr fcc1,1
fail
oke:
set_spr_addr okf,lr
set_fcc 0xe 2
fblglr fcc2,2
fail
okf:
set_spr_addr okg,lr
set_fcc 0xf 3
fblglr fcc3,3
fail
okg:
pass
bad:
fail