)]}'
{
  "commit": "259a2647dc158e196e4e03719cdc6bb0ff657d1d",
  "tree": "d073c6e8df285c0896cdf74c0c7cc12a87fbe21b",
  "parents": [
    "5ec6edd0a215651c4d20984b48095941167e2c0a"
  ],
  "author": {
    "name": "Christoph Müllner",
    "email": "christoph.muellner@vrull.eu",
    "time": "Fri Jun 30 22:44:05 2023 +0200"
  },
  "committer": {
    "name": "Jeff Law",
    "email": "jlaw@ventanamicro",
    "time": "Sat Jul 01 07:28:40 2023 -0600"
  },
  "message": "RISC-V: Add support for the Zvksh ISA extension\n\nZvksh is part of the vector crypto extensions.\n\nThis extension adds the following instructions:\n- vsm3me.vv\n- vsm3c.vi\n\nbfd/ChangeLog:\n\n\t* elfxx-riscv.c (riscv_multi_subset_supports): Add instruction\n\tclass support for Zvksh.\n\t(riscv_multi_subset_supports_ext): Likewise.\n\ngas/ChangeLog:\n\n\t* testsuite/gas/riscv/zvksh.d: New test.\n\t* testsuite/gas/riscv/zvksh.s: New test.\n\ninclude/ChangeLog:\n\n\t* opcode/riscv-opc.h (MATCH_VSM3C_VI): New.\n\t(MASK_VSM3C_VI): New.\n\t(MATCH_VSM3ME_VV): New.\n\t(MASK_VSM3ME_VV): New.\n\t(DECLARE_INSN): New.\n\t* opcode/riscv.h (enum riscv_insn_class): Add instruction class\n\tsupport for Zvksh.\n\nopcodes/ChangeLog:\n\n\t* riscv-opc.c: Add Zvksh instructions.\n\nSigned-off-by: Nathan Huckleberry \u003cnhuck@google.com\u003e\nSigned-off-by: Christoph Müllner \u003cchristoph.muellner@vrull.eu\u003e\n",
  "tree_diff": [
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