)]}'
{
  "commit": "2808125fbb5f9c55f52e863283b7f1c5f0ef1a65",
  "tree": "4074fd934a330a0310876a3fe3ae9aaff81239d0",
  "parents": [
    "edb6b77c755545afb969fcebfa900b07a4b93c94"
  ],
  "author": {
    "name": "Tom Tromey",
    "email": "tromey@adacore.com",
    "time": "Tue May 03 11:23:47 2022 -0600"
  },
  "committer": {
    "name": "Tom Tromey",
    "email": "tromey@adacore.com",
    "time": "Tue Jun 14 09:08:29 2022 -0600"
  },
  "message": "Fix bugs in aarch64-ravenscar-thread.c\n\nWe found a few bugs in aarch64-ravenscar-thread.c.\n\nFirst, some of the register offsets were incorrect.  The \"bb-runtimes\"\nfile for this runtime had the wrong offsets in comments, which GDB\ntook to be correct.  However, those comments didn\u0027t account for\nalignment.  This patch adjusts the offsets.\n\nNext, the \"FPU Saved field\" is not a register -- it is an\nimplementation detail of the runtime.  This is removed.\n\nFinally, I think the FP registers are actually named V0-V31, and the\n\"Q\" names are pseudo-registers.  This patch fixes the comment.\n\n\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "a60471d72756d9ceeb7cb1003fd2a39c05c69608",
      "old_mode": 33188,
      "old_path": "gdb/aarch64-ravenscar-thread.c",
      "new_id": "dc35537e3d589edf66b465d34a56b0a71ea3ea62",
      "new_mode": 33188,
      "new_path": "gdb/aarch64-ravenscar-thread.c"
    }
  ]
}