aarch64: Add new AT system instructions.
This patch adds 3 new AT system instructions through FEAT_ATS1A
feature, which are available by default from Armv9.4-A architecture.
diff --git a/gas/testsuite/gas/aarch64/armv8_9-a-sysregs-bad.l b/gas/testsuite/gas/aarch64/armv8_9-a-sysregs-bad.l
index 63397bc..1b67843 100644
--- a/gas/testsuite/gas/aarch64/armv8_9-a-sysregs-bad.l
+++ b/gas/testsuite/gas/aarch64/armv8_9-a-sysregs-bad.l
@@ -24,3 +24,6 @@
.*: Error: selected processor does not support system register name 'pfar_el1'
.*: Error: selected processor does not support system register name 'pfar_el2'
.*: Error: selected processor does not support system register name 'pfar_el12'
+.*: Error: selected processor does not support system register name 's1e1a'
+.*: Error: selected processor does not support system register name 's1e2a'
+.*: Error: selected processor does not support system register name 's1e3a'
diff --git a/gas/testsuite/gas/aarch64/armv8_9-a-sysregs.d b/gas/testsuite/gas/aarch64/armv8_9-a-sysregs.d
index 3b66e2b..18376bb 100644
--- a/gas/testsuite/gas/aarch64/armv8_9-a-sysregs.d
+++ b/gas/testsuite/gas/aarch64/armv8_9-a-sysregs.d
@@ -31,3 +31,6 @@
.*: d51860a0 msr pfar_el1, x0
.*: d51c60a0 msr pfar_el2, x0
.*: d51d60a0 msr pfar_el12, x0
+.*: d5087941 at s1e1a, x1
+.*: d50c7943 at s1e2a, x3
+.*: d50e7945 at s1e3a, x5
diff --git a/gas/testsuite/gas/aarch64/armv8_9-a-sysregs.s b/gas/testsuite/gas/aarch64/armv8_9-a-sysregs.s
index 9ad0a53..4e494a9 100644
--- a/gas/testsuite/gas/aarch64/armv8_9-a-sysregs.s
+++ b/gas/testsuite/gas/aarch64/armv8_9-a-sysregs.s
@@ -27,3 +27,8 @@
msr PFAR_EL1, x0
msr PFAR_EL2, x0
msr PFAR_EL12, x0
+
+ /* AT. */
+ at s1e1a, x1
+ at s1e2a, x3
+ at s1e3a, x5
diff --git a/include/opcode/aarch64.h b/include/opcode/aarch64.h
index 03ef907..792d6a4 100644
--- a/include/opcode/aarch64.h
+++ b/include/opcode/aarch64.h
@@ -183,6 +183,8 @@
AARCH64_FEATURE_FGT2,
/* Physical Fault Address. */
AARCH64_FEATURE_PFAR,
+ /* Address Translate Stage 1. */
+ AARCH64_FEATURE_ATS1A,
AARCH64_NUM_FEATURES
};
@@ -245,7 +247,8 @@
| AARCH64_FEATBIT (X, RASv2) \
| AARCH64_FEATBIT (X, SCTLR2) \
| AARCH64_FEATBIT (X, FGT2) \
- | AARCH64_FEATBIT (X, PFAR))
+ | AARCH64_FEATBIT (X, PFAR) \
+ | AARCH64_FEATBIT (X, ATS1A))
#define AARCH64_ARCH_V9A_FEATURES(X) (AARCH64_FEATBIT (X, V9A) \
| AARCH64_FEATBIT (X, F16) \
diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c
index e4b3522..4d84071 100644
--- a/opcodes/aarch64-opc.c
+++ b/opcodes/aarch64-opc.c
@@ -4810,6 +4810,9 @@
{ "s1e3w", CPENS (6, C7, C8, 1), F_HASXT },
{ "s1e1rp", CPENS (0, C7, C9, 0), F_HASXT | F_ARCHEXT },
{ "s1e1wp", CPENS (0, C7, C9, 1), F_HASXT | F_ARCHEXT },
+ { "s1e1a", CPENS (0, C7, C9, 2), F_HASXT | F_ARCHEXT },
+ { "s1e2a", CPENS (4, C7, C9, 2), F_HASXT | F_ARCHEXT },
+ { "s1e3a", CPENS (6, C7, C9, 2), F_HASXT | F_ARCHEXT },
{ 0, CPENS(0,0,0,0), 0 }
};
@@ -5041,6 +5044,12 @@
&& AARCH64_CPU_HAS_FEATURE (features, THE))
return true;
+ if ((reg_value == CPENS (0, C7, C9, 2)
+ || reg_value == CPENS (4, C7, C9, 2)
+ || reg_value == CPENS (6, C7, C9, 2))
+ && AARCH64_CPU_HAS_FEATURE (features, ATS1A))
+ return true;
+
return false;
}
