)]}'
{
  "commit": "3009ffe06c8ede5fbb7c9d37dfc731ce2c8fdf45",
  "tree": "11d3fe8d2fe223c8b7dedc4d17c1b9d5126693ea",
  "parents": [
    "354c1c098abe2b5cbc9da9751d29c5e5a0072376"
  ],
  "author": {
    "name": "Tsukasa OI",
    "email": "research_trasio@irq.a4lg.com",
    "time": "Sat Aug 27 13:33:51 2022 +0000"
  },
  "committer": {
    "name": "Tsukasa OI",
    "email": "research_trasio@irq.a4lg.com",
    "time": "Fri Oct 14 05:21:41 2022 +0000"
  },
  "message": "opcodes/riscv-dis.c: Make XLEN variable static\n\nBefore changing the core disassembler, we take care of minor code clarity\nissues and improve readability.\n\nSince xlen variable is not (and should not) used outside riscv-dis.c,\nthis commit makes this variable static.\n\nopcodes/ChangeLog:\n\n\t* riscv-dis.c (xlen): Make this variable static.\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "608670bed7f2870b1f6945f497c7059cb3b21da4",
      "old_mode": 33188,
      "old_path": "opcodes/riscv-dis.c",
      "new_id": "27e1978d42833cf13f09e3623c764fbc2c1ece29",
      "new_mode": 33188,
      "new_path": "opcodes/riscv-dis.c"
    }
  ]
}