Support Intel AVX10.2 satcvt instructions

In this patch, we will support AVX10.2 satcvt instructions. All of them
are new instruction forms. In current documentation, it is still
VCVTTNEBF162I[,U]BS, but it will change to VCVTTBF162I[,U]BS eventually.

In table part, we used temporary <sign> iterator to reduce redundancy.
It definitely could be done for legacy cvt insns, but it is out of this
patch's scope.

gas/ChangeLog:

	* testsuite/gas/i386/i386.exp: Add AVX10.2 tests.
	* testsuite/gas/i386/x86-64.exp: Ditto.
	* testsuite/gas/i386/avx10_2-512-satcvt-intel.d: New test.
	* testsuite/gas/i386/avx10_2-512-satcvt.d: Ditto.
	* testsuite/gas/i386/avx10_2-512-satcvt.s: Ditto.
	* testsuite/gas/i386/avx10_2-256-satcvt-intel.d: Ditto.
	* testsuite/gas/i386/avx10_2-256-satcvt.d: Ditto.
	* testsuite/gas/i386/avx10_2-256-satcvt.s: Ditto.
	* testsuite/gas/i386/x86-64-avx10_2-512-satcvt-intel.d: Ditto.
	* testsuite/gas/i386/x86-64-avx10_2-512-satcvt.d: Ditto.
	* testsuite/gas/i386/x86-64-avx10_2-512-satcvt.s: Ditto.
	* testsuite/gas/i386/x86-64-avx10_2-256-satcvt-intel.d: Ditto.
	* testsuite/gas/i386/x86-64-avx10_2-256-satcvt.d: Ditto.
	* testsuite/gas/i386/x86-64-avx10_2-256-satcvt.s: Ditto.

opcodes/ChangeLog:

	* i386-dis-evex-prefix.h: Add PREFIX_EVEX_MAP5_68, PREFIX_EVEX_MAP5_69,
	PREFIX_EVEX_MAP5_6A, PREFIX_EVEX_MAP5_6B, PREFIX_EVEX_MAP5_6C,
	PREFIX_EVEX_MAP5_6D.
	* i386-dis-evex-w.h: Add EVEX_W_MAP5_6C_P_0, EVEX_W_MAP5_6C_P_2,
	EVEX_W_MAP5_6D_P_0, EVEX_W_MAP5_6D_P_2.
	* i386-dis-evex.h (prefix_table): Add PREFIX_EVEX_MAP5_68,
	* PREFIX_EVEX_MAP5_69, PREFIX_EVEX_MAP5_6A, PREFIX_EVEX_MAP5_6B.
	* i386-dis.c: (PREFIX_EVEX_MAP5_68): New.
	(PREFIX_EVEX_MAP5_69): Ditto.
	(PREFIX_EVEX_MAP5_6A): Ditto.
	(PREFIX_EVEX_MAP5_6B): Ditto.
	(PREFIX_EVEX_MAP5_6C): Ditto.
	(PREFIX_EVEX_MAP5_6D): Ditto.
	(EVEX_MAP5_6C_P_0): Ditto.
	(EVEX_MAP5_6C_P_2): Ditto.
	(EVEX_MAP5_6D_P_0): Ditto.
	(EVEX_MAP5_6D_P_2): Ditto.
	* i386-opc.tbl: Add AVX10.2 instructions.
	* i386-mnem.h: Regenerated.
	* i386-tbl.h: Ditto.

Co-authored-by: Zewei Mo <zewei.mo@intel.com>
Co-authored-by: Haochen Jiang <haochen.jiang@intel.com>
Co-authored-by: Levy Hsu <admin@levyhsu.com>