)]}'
{
  "commit": "38c5aa5e88406193fe184a129cd397bc09c304e2",
  "tree": "e3efcdc0339a3d92042dc49a914acce4a46a6eef",
  "parents": [
    "db3c06bf93f577b9eb40e2cc5d67bfd0671d3c11"
  ],
  "author": {
    "name": "Richard Sandiford",
    "email": "richard.sandiford@arm.com",
    "time": "Thu Mar 30 11:09:08 2023 +0100"
  },
  "committer": {
    "name": "Richard Sandiford",
    "email": "richard.sandiford@arm.com",
    "time": "Thu Mar 30 11:09:08 2023 +0100"
  },
  "message": "aarch64: Make AARCH64_OPDE_REG_LIST take a bitfield\n\nAARCH64_OPDE_REG_LIST took a single operand that specified the\nexpected number of registers.  However, there are quite a few\nSME2 instructions that have both 2-register forms and (separate)\n4-register forms.  If the user tries to use a 3-register list,\nit isn\u0027t obvious which opcode entry they meant.  Saying that we\nexpect 2 registers and saying that we expect 4 registers would\nboth be wrong.\n\nThis patch therefore switches the operand to a bitfield.  If a\nAARCH64_OPDE_REG_LIST is reported against multiple opcode entries,\nthe patch ORs up the expected lengths.\n\nThis has no user-visible effect yet.  A later patch adds more error\nstrings, alongside tests that use them.\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "145e241b13ba77c9a563f1740cb89f9b17316342",
      "old_mode": 33188,
      "old_path": "gas/config/tc-aarch64.c",
      "new_id": "a57cc2bc080c5d34783f04300da1a19e9df350e2",
      "new_mode": 33188,
      "new_path": "gas/config/tc-aarch64.c"
    },
    {
      "type": "modify",
      "old_id": "dfffbf6f6e5f31b9c04dd0740f59cd4b9f982319",
      "old_mode": 33188,
      "old_path": "opcodes/aarch64-opc.c",
      "new_id": "590d227fde362291bbe15359f739c79464a5b076",
      "new_mode": 33188,
      "new_path": "opcodes/aarch64-opc.c"
    }
  ]
}