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; Fujitsu FRV opcode support, for GNU Binutils. -*- Scheme -*-
;
; Copyright 2000, 2001, 2003, 2004, 2007, 2009 Free Software Foundation, Inc.
;
; Contributed by Red Hat Inc; developed under contract from Fujitsu.
;
; This file is part of the GNU Binutils.
;
; This program is free software; you can redistribute it and/or modify
; it under the terms of the GNU General Public License as published by
; the Free Software Foundation; either version 3 of the License, or
; (at your option) any later version.
;
; This program is distributed in the hope that it will be useful,
; but WITHOUT ANY WARRANTY; without even the implied warranty of
; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
; GNU General Public License for more details.
;
; You should have received a copy of the GNU General Public License
; along with this program; if not, write to the Free Software
; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
; MA 02110-1301, USA.
(include "simplify.inc")
; define-arch must appear first
(define-arch
(name frv) ; name of cpu architecture
(comment "Fujitsu FRV")
(insn-lsb0? #t)
(machs frv fr550 fr500 fr450 fr400 tomcat simple)
(isas frv)
)
(define-isa
(name frv)
(base-insn-bitsize 32)
; Initial bitnumbers to decode insns by.
(decode-assist (24 23 22 21 20 19 18))
(liw-insns 1) ; The frv fetches up to 1 insns at a time.
(parallel-insns 8) ; The frv executes up to 8 insns at a time.
)
; Cpu family definitions.
;
(define-cpu
; cpu names must be distinct from the architecture name and machine names.
; The "b" suffix stands for "base" and is the convention.
; The "f" suffix stands for "family" and is the convention.
(name frvbf)
(comment "Fujitsu FRV base family")
(endian big)
(word-bitsize 32)
)
; Generic FR-V machine. Supports the entire architecture
(define-mach
(name frv)
(comment "Generic FRV cpu")
(cpu frvbf)
)
(define-model
(name frv) (comment "Generic FRV model") (attrs)
(mach frv)
(pipeline all "" () ((fetch) (decode) (execute) (writeback)))
; `state' is a list of variables for recording model state
; (state)
(unit u-exec "Execution Unit" ()
1 1 ; issue done
() ; state
() ; inputs
() ; outputs
() ; profile action (default)
)
)
; FR550 machine
(define-mach
(name fr550)
(comment "FR550 cpu")
(cpu frvbf)
)
(define-model
(name fr550) (comment "FR550 model") (attrs)
(mach fr550)
(pipeline all "" () ((fetch) (decode) (execute) (writeback)))
; `state' is a list of variables for recording model state
(state
; State items
; These are all masks with each bit representing one register.
(prev-fr-load DI) ; Previous use of FR register was target of a load
(prev-fr-complex-1 DI) ; Previous use of FR register has variable latency
(prev-fr-complex-2 DI) ; Previous use of FR register has variable latency
(prev-ccr-complex DI) ; Previous use of CCR register has variable latency
(prev-acc-mmac DI) ; Previous use of ACC register was a MMAC category
(cur-fr-load DI) ; Current use of FR register was target of a load
(cur-fr-complex-1 DI) ; Current use of FR register has variable latency
(cur-fr-complex-2 DI) ; Current use of FR register has variable latency
(cur-ccr-complex SI) ; Current use of CCR register has variable latency
(cur-acc-mmac DI) ; Current use of ACC register was a MMAC category
)
; Basic unit for instructions with no latency penalties
(unit u-exec "Execution Unit" ()
1 1 ; issue done
() ; state
() ; inputs
() ; outputs
() ; profile action (default)
)
; Basic integer insn unit
(unit u-integer "Integer Unit" ()
1 1 ; issue done
() ; state
((GRi INT -1) (GRj INT -1)) ; inputs
((GRk INT -1) (ICCi_1 INT -1)) ; outputs
() ; profile action (default)
)
; Integer multiplication unit
(unit u-imul "Integer Multiplication Unit" ()
1 1 ; issue done
() ; state
((GRi INT -1) (GRj INT -1)) ; inputs
((GRdoublek INT -1) (ICCi_1 INT -1)) ; outputs
() ; profile action (default)
)
; Integer division unit
(unit u-idiv "Integer Division Unit" ()
1 1 ; issue done
() ; state
((GRi INT -1) (GRj INT -1)) ; inputs
((GRk INT -1) (ICCi_1 INT -1)) ; outputs
() ; profile action (default)
)
; Branch unit
(unit u-branch "Branch Unit" ()
1 1 ; issue done
() ; state
((GRi INT -1) (GRj INT -1)
(ICCi_2 INT -1) (FCCi_2 INT -1)) ; inputs
((pc)) ; outputs
() ; profile action (default)
)
; Trap unit
(unit u-trap "Trap Unit" ()
1 1 ; issue done
() ; state
((GRi INT -1) (GRj INT -1)
(ICCi_2 INT -1) (FCCi_2 INT -1)) ; inputs
() ; outputs
() ; profile action (default)
)
; Condition code check unit
(unit u-check "Check Unit" ()
1 1 ; issue done
() ; state
((ICCi_3 INT -1) (FCCi_3 INT -1)) ; inputs
() ; outputs
() ; profile action (default)
)
; Float Arithmetic unit
(unit u-float-arith "Float Arithmetic unit" ()
1 1 ; issue done
() ; state
((FRi INT -1) (FRj INT -1) ; inputs
(FRdoublei INT -1) (FRdoublej INT -1)) ; inputs
((FRk INT -1) (FRdoublek INT -1)) ; outputs
() ; profile action (default)
)
; Float Dual Arithmetic unit
(unit u-float-dual-arith "Float Arithmetic unit" ()
; This unit has a 2 cycle penalty -- see table 14-14 in the fr550 LSI
1 3 ; issue done
() ; state
((FRi INT -1) (FRj INT -1) ; inputs
(FRdoublei INT -1) (FRdoublej INT -1)) ; inputs
((FRk INT -1) (FRdoublek INT -1)) ; outputs
() ; profile action (default)
)
; Float Div unit
(unit u-float-div "Float Div unit" ()
1 1 ; issue done
() ; state
((FRi INT -1) (FRj INT -1)) ; inputs
((FRk INT -1)) ; outputs
() ; profile action (default)
)
; Float Square Root unit
(unit u-float-sqrt "Float Square Root unit" ()
1 1 ; issue done
() ; state
((FRj INT -1) (FRdoublej INT -1)) ; inputs
((FRk INT -1) (FRdoublek INT -1)) ; outputs
() ; profile action (default)
)
; Float Compare unit
(unit u-float-compare "Float Compare unit" ()
1 1 ; issue done
() ; state
((FRi INT -1) (FRj INT -1)
(FRdoublei INT -1) (FRdoublej INT -1)) ; inputs
((FCCi_2 INT -1)) ; outputs
() ; profile action (default)
)
; Dual Float Compare unit
(unit u-float-dual-compare "Float Dual Compare unit" ()
; This unit has a 2 cycle penalty -- see table 14-14 in the fr550 LSI
1 3 ; issue done
() ; state
((FRi INT -1) (FRj INT -1)) ; inputs
((FCCi_2 INT -1)) ; outputs
() ; profile action (default)
)
; FR Move to GR unit
(unit u-fr2gr "FR Move to GR Unit" ()
1 1 ; issue done
() ; state
((FRintk INT -1)) ; inputs
((GRj INT -1)) ; outputs
() ; profile action (default)
)
; GR Move to FR unit
(unit u-gr2fr "GR Move to FR Unit" ()
1 1 ; issue done
() ; state
((GRj INT -1)) ; inputs
((FRintk INT -1)) ; outputs
() ; profile action (default)
)
; SPR Move to GR unit
(unit u-spr2gr "SPR Move to GR Unit" ()
1 1 ; issue done
() ; state
((spr INT -1)) ; inputs
((GRj INT -1)) ; outputs
() ; profile action (default)
)
; GR Move to SPR unit
(unit u-gr2spr "GR Move to SPR Unit" ()
1 1 ; issue done
() ; state
((GRj INT -1)) ; inputs
((spr INT -1)) ; outputs
() ; profile action (default)
)
; GR set half unit
(unit u-set-hilo "GR Set Half" ()
1 1 ; issue done
() ; state
() ; inputs
((GRkhi INT -1) (GRklo INT -1)) ; outputs
() ; profile action (default)
)
; GR load unit
(unit u-gr-load "GR Load Unit" ()
1 1 ; issue done
() ; state
((GRi INT -1) (GRj INT -1)) ; inputs
((GRk INT -1) (GRdoublek INT -1)) ; outputs
() ; profile action (default)
)
; GR store unit
(unit u-gr-store "GR Store Unit" ()
1 1 ; issue done
() ; state
((GRi INT -1) (GRj INT -1) (GRk INT -1) (GRdoublek INT -1)) ; inputs
() ; outputs
() ; profile action (default)
)
; FR load unit
(unit u-fr-load "FR Load Unit" ()
1 1 ; issue done
() ; state
((GRi INT -1) (GRj INT -1)) ; inputs
((FRintk INT -1) (FRdoublek INT -1)) ; outputs
() ; profile action (default)
)
; FR store unit
(unit u-fr-store "FR Store Unit" ()
1 1 ; issue done
() ; state
((GRi INT -1) (GRj INT -1) (FRintk INT -1) (FRdoublek INT -1)) ; inputs
() ; outputs
() ; profile action (default)
)
; Swap unit
(unit u-swap "Swap Unit" ()
1 1 ; issue done
() ; state
((GRi INT -1) (GRj INT -1)) ; inputs
((GRk INT -1)) ; outputs
() ; profile action (default)
)
; FR Move to FR unit
(unit u-fr2fr "FR Move to FR Unit" ()
1 1 ; issue done
() ; state
((FRi INT -1)) ; inputs
((FRk INT -1)) ; outputs
() ; profile action (default)
)
; Clrgr unit
(unit u-clrgr "Clrgr Unit" ()
1 1 ; issue done
() ; state
((GRk INT -1)) ; inputs
() ; outputs
() ; profile action (default)
)
; Clrfr unit
(unit u-clrfr "Clrfr Unit" ()
1 1 ; issue done
() ; state
((FRk INT -1)) ; inputs
() ; outputs
() ; profile action (default)
)
; Insn cache invalidate unit
(unit u-ici "Insn cache invalidate unit" ()
1 1 ; issue done
() ; state
((GRi INT -1) (GRj INT -1)) ; inputs
() ; outputs
() ; profile action (default)
)
; Data cache invalidate unit
(unit u-dci "Data cache invalidate unit" ()
1 1 ; issue done
() ; state
((GRi INT -1) (GRj INT -1)) ; inputs
() ; outputs
() ; profile action (default)
)
; Data cache flush unit
(unit u-dcf "Data cache flush unit" ()
1 1 ; issue done
() ; state
((GRi INT -1) (GRj INT -1)) ; inputs
() ; outputs
() ; profile action (default)
)
; Insn cache preload unit
(unit u-icpl "Insn cache preload unit" ()
1 1 ; issue done
() ; state
((GRi INT -1) (GRj INT -1)) ; inputs
() ; outputs
() ; profile action (default)
)
; Data cache preload unit
(unit u-dcpl "Data cache preload unit" ()
1 1 ; issue done
() ; state
((GRi INT -1) (GRj INT -1)) ; inputs
() ; outputs
() ; profile action (default)
)
; Insn cache unlock unit
(unit u-icul "Insn cache unlock unit" ()
1 1 ; issue done
() ; state
((GRi INT -1) (GRj INT -1)) ; inputs
() ; outputs
() ; profile action (default)
)
; Data cache unlock unit
(unit u-dcul "Data cache unlock unit" ()
1 1 ; issue done
() ; state
((GRi INT -1) (GRj INT -1)) ; inputs
() ; outputs
() ; profile action (default)
)
; commit unit
(unit u-commit "Commit Unit" ()
1 1 ; issue done
() ; state
((GRk INT -1) (FRk INT -1)) ; inputs
() ; outputs
() ; profile action (default)
)
; Float Conversion unit
(unit u-float-convert "Float Conversion unit" ()
1 1 ; issue done
() ; state
((FRj INT -1) (FRintj INT -1) (FRdoublej INT -1)) ; inputs
((FRk INT -1) (FRintk INT -1) (FRdoublek INT -1)) ; outputs
() ; profile action (default)
)
; Media units
(unit u-media "Media unit" ()
1 1 ; issue done
() ; state
((FRinti INT -1) (FRintj INT -1)) ; inputs
((FRintk INT -1)) ; outputs
() ; profile action (default)
)
(unit u-media-quad "Media-quad unit" ()
1 1 ; issue done
() ; state
((FRintieven INT -1) (FRintjeven INT -1)) ; inputs
((FRintkeven INT -1)) ; outputs
() ; profile action (default)
)
(unit u-media-dual-expand "Media Dual Expand unit" ()
1 1 ; issue done
() ; state
((FRinti INT -1)) ; inputs
((FRintkeven INT -1)) ; outputs
() ; profile action (default)
)
(unit u-media-3-dual "Media-3-dual unit" ()
1 1 ; issue done
() ; state
((FRinti INT -1)) ; inputs
((FRintk INT -1)) ; outputs
() ; profile action (default)
)
(unit u-media-3-acc "Media unit for M-3 using ACC" ()
1 1 ; issue done
() ; state
((FRintj INT -1) (ACC40Si INT -1)) ; inputs
((FRintk INT -1)) ; outputs
() ; profile action (default)
)
(unit u-media-3-acc-dual "Media-3-acc-dual unit" ()
1 1 ; issue done
() ; state
((ACC40Si INT -1)) ; inputs
((FRintkeven INT -1)) ; outputs
() ; profile action (default)
)
(unit u-media-3-wtacc "Media-3-wtacc unit" ()
1 1 ; issue done
() ; state
((FRinti INT -1) (ACC40Sk INT -1)) ; inputs
() ; outputs
() ; profile action (default)
)
(unit u-media-3-mclracc "Media-3-mclracc unit" ()
1 1 ; issue done
() ; state
() ; inputs
() ; outputs
() ; profile action (default)
)
(unit u-media-set "Media set" ()
1 1 ; issue done
() ; state
() ; inputs
((FRintk INT -1)) ; outputs
() ; profile action (default)
)
(unit u-media-4 "Media-4 unit" ()
1 1 ; issue done
() ; state
((FRinti INT -1) (FRintj INT -1)) ; inputs
((ACC40Sk INT -1) (ACC40Uk INT -1)) ; outputs
() ; profile action (default)
)
(unit u-media-4-acc "Media-4-acc unit" ()
1 1 ; issue done
() ; state
((ACC40Si INT -1)) ; inputs
((ACC40Sk INT -1)) ; outputs
() ; profile action (default)
)
(unit u-media-4-acc-dual "Media-4-acc-dual unit" ()
1 1 ; issue done
() ; state
((ACC40Si INT -1)) ; inputs
((ACC40Sk INT -1)) ; outputs
() ; profile action (default)
)
(unit u-media-4-add-sub "Media-4-add-sub unit" ()
1 1 ; issue done
() ; state
((ACC40Si INT -1)) ; inputs
((ACC40Sk INT -1)) ; outputs
() ; profile action (default)
)
(unit u-media-4-add-sub-dual "Media-4-add-sub-dual unit" ()
1 1 ; issue done
() ; state
((ACC40Si INT -1)) ; inputs
((ACC40Sk INT -1)) ; outputs
() ; profile action (default)
)
(unit u-media-4-quad "Media-4-quad unit" ()
1 1 ; issue done
() ; state
((FRintieven INT -1) (FRintjeven INT -1)) ; inputs
((ACC40Sk INT -1) (ACC40Uk INT -1)) ; outputs
() ; profile action (default)
)
)
; FR500 machine.
(define-mach
(name fr500)
(comment "FR500 cpu")
(cpu frvbf)
)
(define-model
(name fr500) (comment "FR500 model") (attrs)
(mach fr500)
(pipeline all "" () ((fetch) (decode) (execute) (writeback)))
; `state' is a list of variables for recording model state
(state
; State items
; These are all masks with each bit representing one register.
(prev-fpop DI) ; Previous use of FR register was floating point insn
(prev-media DI) ; Previous use of FR register was a media insn
(prev-cc-complex DI) ; Previous use of ICC register was not simple
(cur-fpop DI) ; Current use of FR register was floating point insn
(cur-media DI) ; Current use of FR register was a media insn
(cur-cc-complex DI) ; Current use of ICC register was not simple
)
; Basic unit for instructions with no latency penalties
(unit u-exec "Execution Unit" ()
1 1 ; issue done
() ; state
() ; inputs
() ; outputs
() ; profile action (default)
)
; Basic integer insn unit
(unit u-integer "Integer Unit" ()
1 1 ; issue done
() ; state
((GRi INT -1) (GRj INT -1)) ; inputs
((GRk INT -1) (ICCi_1 INT -1)) ; outputs
() ; profile action (default)
)
; Integer multiplication unit
(unit u-imul "Integer Multiplication Unit" ()
1 1 ; issue done
() ; state
((GRi INT -1) (GRj INT -1)) ; inputs
((GRdoublek INT -1) (ICCi_1 INT -1)) ; outputs
() ; profile action (default)
)
; Integer division unit
(unit u-idiv "Integer Division Unit" ()
1 1 ; issue done
() ; state
((GRi INT -1) (GRj INT -1)) ; inputs
((GRk INT -1) (ICCi_1 INT -1)) ; outputs
() ; profile action (default)
)
; Branch unit
(unit u-branch "Branch Unit" ()
1 1 ; issue done
() ; state
((GRi INT -1) (GRj INT -1)
(ICCi_2 INT -1) (FCCi_2 INT -1)) ; inputs
((pc)) ; outputs
() ; profile action (default)
)
; Trap unit
(unit u-trap "Trap Unit" ()
1 1 ; issue done
() ; state
((GRi INT -1) (GRj INT -1)
(ICCi_2 INT -1) (FCCi_2 INT -1)) ; inputs
() ; outputs
() ; profile action (default)
)
; Condition code check unit
(unit u-check "Check Unit" ()
1 1 ; issue done
() ; state
((ICCi_3 INT -1) (FCCi_3 INT -1)) ; inputs
() ; outputs
() ; profile action (default)
)
; Clrgr unit
(unit u-clrgr "Clrgr Unit" ()
1 1 ; issue done
() ; state
((GRk INT -1)) ; inputs
() ; outputs
() ; profile action (default)
)
; Clrfr unit
(unit u-clrfr "Clrfr Unit" ()
1 1 ; issue done
() ; state
((FRk INT -1)) ; inputs
() ; outputs
() ; profile action (default)
)
; GR set half unit
(unit u-set-hilo "GR Set Half" ()
1 1 ; issue done
() ; state
() ; inputs
((GRkhi INT -1) (GRklo INT -1)) ; outputs
() ; profile action (default)
)
; GR load unit -- TODO doesn't handle quad
(unit u-gr-load "GR Load Unit" ()
1 1 ; issue done
() ; state
((GRi INT -1) (GRj INT -1)) ; inputs
((GRk INT -1) (GRdoublek INT -1)) ; outputs
() ; profile action (default)
)
; GR store unit -- TODO doesn't handle quad
(unit u-gr-store "GR Store Unit" ()
1 1 ; issue done
() ; state
((GRi INT -1) (GRj INT -1) (GRk INT -1) (GRdoublek INT -1)) ; inputs
() ; outputs
() ; profile action (default)
)
; GR recovering store unit -- TODO doesn't handle quad
(unit u-gr-r-store "GR Recovering Store Unit" ()
1 1 ; issue done
() ; state
((GRi INT -1) (GRj INT -1) (GRk INT -1) (GRdoublek INT -1)) ; inputs
() ; outputs
() ; profile action (default)
)
; FR load unit -- TODO doesn't handle quad
(unit u-fr-load "FR Load Unit" ()
1 1 ; issue done
() ; state
((GRi INT -1) (GRj INT -1)) ; inputs
((FRintk INT -1) (FRdoublek INT -1)) ; outputs
() ; profile action (default)
)
; FR store unit -- TODO doesn't handle quad
(unit u-fr-store "FR Store Unit" ()
1 1 ; issue done
() ; state
((GRi INT -1) (GRj INT -1) (FRintk INT -1) (FRdoublek INT -1)) ; inputs
() ; outputs
() ; profile action (default)
)
; FR recovering store unit -- TODO doesn't handle quad
(unit u-fr-r-store "FR Recovering Store Unit" ()
1 1 ; issue done
() ; state
((GRi INT -1) (GRj INT -1) (FRintk INT -1) (FRdoublek INT -1)) ; inputs
() ; outputs
() ; profile action (default)
)
; Swap unit
(unit u-swap "Swap Unit" ()
1 1 ; issue done
() ; state
((GRi INT -1) (GRj INT -1)) ; inputs
((GRk INT -1)) ; outputs
() ; profile action (default)
)
; FR Move to FR unit
(unit u-fr2fr "FR Move to FR Unit" ()
1 1 ; issue done
() ; state
((FRi INT -1)) ; inputs
((FRk INT -1)) ; outputs
() ; profile action (default)
)
; FR Move to GR unit
(unit u-fr2gr "FR Move to GR Unit" ()
1 1 ; issue done
() ; state
((FRintk INT -1)) ; inputs
((GRj INT -1)) ; outputs
() ; profile action (default)
)
; SPR Move to GR unit
(unit u-spr2gr "SPR Move to GR Unit" ()
1 1 ; issue done
() ; state
((spr INT -1)) ; inputs
((GRj INT -1)) ; outputs
() ; profile action (default)
)
; GR Move to FR unit
(unit u-gr2fr "GR Move to FR Unit" ()
1 1 ; issue done
() ; state
((GRj INT -1)) ; inputs
((FRintk INT -1)) ; outputs
() ; profile action (default)
)
; GR Move to SPR unit
(unit u-gr2spr "GR Move to SPR Unit" ()
1 1 ; issue done
() ; state
((GRj INT -1)) ; inputs
((spr INT -1)) ; outputs
() ; profile action (default)
)
; Float Arithmetic unit
(unit u-float-arith "Float Arithmetic unit" ()
1 1 ; issue done
() ; state
((FRi INT -1) (FRj INT -1) ; inputs
(FRdoublei INT -1) (FRdoublej INT -1)) ; inputs
((FRk INT -1) (FRdoublek INT -1)) ; outputs
() ; profile action (default)
)
; Float Dual Arithmetic unit
(unit u-float-dual-arith "Float Arithmetic unit" ()
1 1 ; issue done
() ; state
((FRi INT -1) (FRj INT -1) ; inputs
(FRdoublei INT -1) (FRdoublej INT -1)) ; inputs
((FRk INT -1) (FRdoublek INT -1)) ; outputs
() ; profile action (default)
)
; Float Div unit
(unit u-float-div "Float Div unit" ()
1 1 ; issue done
() ; state
((FRi INT -1) (FRj INT -1)) ; inputs
((FRk INT -1)) ; outputs
() ; profile action (default)
)
; Float Square Root unit
(unit u-float-sqrt "Float Square Root unit" ()
1 1 ; issue done
() ; state
((FRj INT -1) (FRdoublej INT -1)) ; inputs
((FRk INT -1) (FRdoublek INT -1)) ; outputs
() ; profile action (default)
)
; Float Dual Square Root unit
(unit u-float-dual-sqrt "Float Dual Square Root unit" ()
1 1 ; issue done
() ; state
((FRj INT -1)) ; inputs
((FRk INT -1)) ; outputs
() ; profile action (default)
)
; Float Compare unit
(unit u-float-compare "Float Compare unit" ()
1 1 ; issue done
() ; state
((FRi INT -1) (FRj INT -1)
(FRdoublei INT -1) (FRdoublej INT -1)) ; inputs
((FCCi_2 INT -1)) ; outputs
() ; profile action (default)
)
; Dual Float Compare unit
(unit u-float-dual-compare "Float Dual Compare unit" ()
1 1 ; issue done
() ; state
((FRi INT -1) (FRj INT -1)) ; inputs
((FCCi_2 INT -1)) ; outputs
() ; profile action (default)
)
; Float Conversion unit
(unit u-float-convert "Float Conversion unit" ()
1 1 ; issue done
() ; state
((FRj INT -1) (FRintj INT -1) (FRdoublej INT -1)) ; inputs
((FRk INT -1) (FRintk INT -1) (FRdoublek INT -1)) ; outputs
() ; profile action (default)
)
; Dual Float Conversion unit
(unit u-float-dual-convert "Float Dual Conversion unit" ()
1 1 ; issue done
() ; state
((FRj INT -1) (FRintj INT -1)) ; inputs
((FRk INT -1) (FRintk INT -1)) ; outputs
() ; profile action (default)
)
; Media unit
(unit u-media "Media unit" ()
1 1 ; issue done
() ; state
((FRinti INT -1) (FRintj INT -1) (ACC40Si INT -1) (ACCGi INT -1)) ; inputs
((FRintk INT -1) (ACC40Sk INT -1) (ACC40Uk INT -1) (ACCGk INT -1)) ; outputs
() ; profile action (default)
)
; Media Quad Arithmetic unit
(unit u-media-quad-arith "Media Quad Arithmetic unit" ()
1 1 ; issue done
() ; state
((FRinti INT -1) (FRintj INT -1)) ; inputs
((FRintk INT -1)) ; outputs
() ; profile action (default)
)
; Media Dual Multiplication unit
(unit u-media-dual-mul "Media Dual Multiplication unit" ()
1 1 ; issue done
() ; state
((FRinti INT -1) (FRintj INT -1)) ; inputs
((ACC40Sk INT -1) (ACC40Uk INT -1)) ; outputs
() ; profile action (default)
)
; Media Quad Multiplication unit
(unit u-media-quad-mul "Media Quad Multiplication unit" ()
1 1 ; issue done
() ; state
((FRinti INT -1) (FRintj INT -1)) ; inputs
((ACC40Sk INT -1) (ACC40Uk INT -1)) ; outputs
() ; profile action (default)
)
; Media Quad Complex unit
(unit u-media-quad-complex "Media Quad Complex unit" ()
1 1 ; issue done
() ; state
((FRinti INT -1) (FRintj INT -1)) ; inputs
((ACC40Sk INT -1)) ; outputs
() ; profile action (default)
)
; Media Dual Expand unit
(unit u-media-dual-expand "Media Dual Expand unit" ()
1 1 ; issue done
() ; state
((FRinti INT -1)) ; inputs
((FRintk INT -1)) ; outputs
() ; profile action (default)
)
; Media Dual Unpack unit
(unit u-media-dual-unpack "Media Dual Unpack unit" ()
1 1 ; issue done
() ; state
((FRinti INT -1)) ; inputs
((FRintk INT -1)) ; outputs
() ; profile action (default)
)
; Media Dual byte to half unit
(unit u-media-dual-btoh "Media Byte to byte" ()
1 1 ; issue done
() ; state
((FRintj INT -1)) ; inputs
((FRintk INT -1)) ; outputs
() ; profile action (default)
)
; Media Dual half to byte unit
(unit u-media-dual-htob "Media Half to byte" ()
1 1 ; issue done
() ; state
((FRintj INT -1)) ; inputs
((FRintk INT -1)) ; outputs
() ; profile action (default)
)
; Media Dual byte to half unit extended
(unit u-media-dual-btohe "Media Byte to byte extended" ()
1 1 ; issue done
() ; state
((FRintj INT -1)) ; inputs
((FRintk INT -1)) ; outputs
() ; profile action (default)
)
; Barrier unit
(unit u-barrier "Barrier unit" ()
1 1 ; issue done
() ; state
() ; inputs
() ; outputs
() ; profile action (default)
)
; Memory Barrier unit
(unit u-membar "Memory Barrier unit" ()
1 1 ; issue done
() ; state
() ; inputs
() ; outputs
() ; profile action (default)
)
; Insn cache invalidate unit
(unit u-ici "Insn cache invalidate unit" ()
1 1 ; issue done
() ; state
((GRi INT -1) (GRj INT -1)) ; inputs
() ; outputs
() ; profile action (default)
)
; Data cache invalidate unit
(unit u-dci "Data cache invalidate unit" ()
1 1 ; issue done
() ; state
((GRi INT -1) (GRj INT -1)) ; inputs
() ; outputs
() ; profile action (default)
)
; Data cache flush unit
(unit u-dcf "Data cache flush unit" ()
1 1 ; issue done
() ; state
((GRi INT -1) (GRj INT -1)) ; inputs
() ; outputs
() ; profile action (default)
)
; Insn cache preload unit
(unit u-icpl "Insn cache preload unit" ()
1 1 ; issue done
() ; state
((GRi INT -1) (GRj INT -1)) ; inputs
() ; outputs
() ; profile action (default)
)
; Data cache preload unit
(unit u-dcpl "Data cache preload unit" ()
1 1 ; issue done
() ; state
((GRi INT -1) (GRj INT -1)) ; inputs
() ; outputs
() ; profile action (default)
)
; Insn cache unlock unit
(unit u-icul "Insn cache unlock unit" ()
1 1 ; issue done
() ; state
((GRi INT -1) (GRj INT -1)) ; inputs
() ; outputs
() ; profile action (default)
)
; Data cache unlock unit
(unit u-dcul "Data cache unlock unit" ()
1 1 ; issue done
() ; state
((GRi INT -1) (GRj INT -1)) ; inputs
() ; outputs
() ; profile action (default)
)
; commit unit
(unit u-commit "Commit Unit" ()
1 1 ; issue done
() ; state
((GRk INT -1) (FRk INT -1)) ; inputs
() ; outputs
() ; profile action (default)
)
)
; Tomcat machine. Early version of fr500 machine
(define-mach
(name tomcat)
(comment "Tomcat -- early version of fr500")
(cpu frvbf)
)
(define-model
(name tomcat) (comment "Tomcat model") (attrs)
(mach tomcat)
(pipeline all "" () ((fetch) (decode) (execute) (writeback)))
; `state' is a list of variables for recording model state
; (state)
(unit u-exec "Execution Unit" ()
1 1 ; issue done
() ; state
() ; inputs
() ; outputs
() ; profile action (default)
)
)
; FR400 machine
(define-mach
(name fr400)
(comment "FR400 cpu")
(cpu frvbf)
)
(define-model
(name fr400) (comment "FR400 model") (attrs)
(mach fr400)
(pipeline all "" () ((fetch) (decode) (execute) (writeback)))
; `state' is a list of variables for recording model state
(state
; State items
; These are all masks with each bit representing one register.
(prev-fp-load DI) ; Previous use of FR register was floating point load
(prev-fr-p4 DI) ; Previous use of FR register was media unit 4
(prev-fr-p6 DI) ; Previous use of FR register was media unit 6
(prev-acc-p2 DI) ; Previous use of ACC register was media unit 2
(prev-acc-p4 DI) ; Previous use of ACC register was media unit 4
(cur-fp-load DI) ; Current use of FR register is floating point load
(cur-fr-p4 DI) ; Current use of FR register is media unit 4
(cur-fr-p6 DI) ; Current use of FR register is media unit 6
(cur-acc-p2 DI) ; Current use of ACC register is media unit 2
(cur-acc-p4 DI) ; Current use of ACC register is media unit 4
)
(unit u-exec "Execution Unit" ()
1 1 ; issue done
() ; state
() ; inputs
() ; outputs
() ; profile action (default)
)
; Basic integer insn unit
(unit u-integer "Integer Unit" ()
1 1 ; issue done
() ; state
((GRi INT -1) (GRj INT -1)) ; inputs
((GRk INT -1) (ICCi_1 INT -1)) ; outputs
() ; profile action (default)
)
; Integer multiplication unit
(unit u-imul "Integer Multiplication Unit" ()
1 1 ; issue done
() ; state
((GRi INT -1) (GRj INT -1)) ; inputs
((GRdoublek INT -1) (ICCi_1 INT -1)) ; outputs
() ; profile action (default)
)
; Integer division unit
(unit u-idiv "Integer Division Unit" ()
1 1 ; issue done
() ; state
((GRi INT -1) (GRj INT -1)) ; inputs
((GRk INT -1) (ICCi_1 INT -1)) ; outputs
() ; profile action (default)
)
; Branch unit
(unit u-branch "Branch Unit" ()
1 1 ; issue done
() ; state
((GRi INT -1) (GRj INT -1)
(ICCi_2 INT -1) (FCCi_2 INT -1)) ; inputs
((pc)) ; outputs
() ; profile action (default)
)
; Trap unit
(unit u-trap "Trap Unit" ()
1 1 ; issue done
() ; state
((GRi INT -1) (GRj INT -1)
(ICCi_2 INT -1) (FCCi_2 INT -1)) ; inputs
() ; outputs
() ; profile action (default)
)
; Condition code check unit
(unit u-check "Check Unit" ()
1 1 ; issue done
() ; state
((ICCi_3 INT -1) (FCCi_3 INT -1)) ; inputs
() ; outputs
() ; profile action (default)
)
; GR set half unit
(unit u-set-hilo "GR Set Half" ()
1 1 ; issue done
() ; state
() ; inputs
((GRkhi INT -1) (GRklo INT -1)) ; outputs
() ; profile action (default)
)
; GR load unit -- TODO doesn't handle quad
(unit u-gr-load "GR Load Unit" ()
1 1 ; issue done
() ; state
((GRi INT -1) (GRj INT -1)) ; inputs
((GRk INT -1) (GRdoublek INT -1)) ; outputs
() ; profile action (default)
)
; GR store unit -- TODO doesn't handle quad
(unit u-gr-store "GR Store Unit" ()
1 1 ; issue done
() ; state
((GRi INT -1) (GRj INT -1) (GRk INT -1) (GRdoublek INT -1)) ; inputs
() ; outputs
() ; profile action (default)
)
; FR load unit -- TODO doesn't handle quad
(unit u-fr-load "FR Load Unit" ()
1 1 ; issue done
() ; state
((GRi INT -1) (GRj INT -1)) ; inputs
((FRintk INT -1) (FRdoublek INT -1)) ; outputs
() ; profile action (default)
)
; FR store unit -- TODO doesn't handle quad
(unit u-fr-store "FR Store Unit" ()
1 1 ; issue done
() ; state
((GRi INT -1) (GRj INT -1) (FRintk INT -1) (FRdoublek INT -1)) ; inputs
() ; outputs
() ; profile action (default)
)
; Swap unit
(unit u-swap "Swap Unit" ()
1 1 ; issue done
() ; state
((GRi INT -1) (GRj INT -1)) ; inputs
((GRk INT -1)) ; outputs
() ; profile action (default)
)
; FR Move to GR unit
(unit u-fr2gr "FR Move to GR Unit" ()
1 1 ; issue done
() ; state
((FRintk INT -1)) ; inputs
((GRj INT -1)) ; outputs
() ; profile action (default)
)
; SPR Move to GR unit
(unit u-spr2gr "SPR Move to GR Unit" ()
1 1 ; issue done
() ; state
((spr INT -1)) ; inputs
((GRj INT -1)) ; outputs
() ; profile action (default)
)
; GR Move to FR unit
(unit u-gr2fr "GR Move to FR Unit" ()
1 1 ; issue done
() ; state
((GRj INT -1)) ; inputs
((FRintk INT -1)) ; outputs
() ; profile action (default)
)
; GR Move to SPR unit
(unit u-gr2spr "GR Move to SPR Unit" ()
1 1 ; issue done
() ; state
((GRj INT -1)) ; inputs
((spr INT -1)) ; outputs
() ; profile action (default)
)
; Media unit M1 -- see table 13-8 in the fr400 LSI
(unit u-media-1 "Media-1 unit" ()
1 1 ; issue done
() ; state
((FRinti INT -1) (FRintj INT -1)) ; inputs
((FRintk INT -1)) ; outputs
() ; profile action (default)
)
(unit u-media-1-quad "Media-1-quad unit" ()
1 1 ; issue done
() ; state
((FRinti INT -1) (FRintj INT -1)) ; inputs
((FRintk INT -1)) ; outputs
() ; profile action (default)
)
(unit u-media-hilo "Media-hilo unit -- a variation of the Media-1 unit" ()
1 1 ; issue done
() ; state
() ; inputs
((FRkhi INT -1) (FRklo INT -1)) ; outputs
() ; profile action (default)
)
; Media unit M2 -- see table 13-8 in the fr400 LSI
(unit u-media-2 "Media-2 unit" ()
1 1 ; issue done
() ; state
((FRinti INT -1) (FRintj INT -1)) ; inputs
((ACC40Sk INT -1) (ACC40Uk INT -1)) ; outputs
() ; profile action (default)
)
(unit u-media-2-quad "Media-2-quad unit" ()
1 1 ; issue done
() ; state
((FRinti INT -1) (FRintj INT -1)) ; inputs
((ACC40Sk INT -1) (ACC40Uk INT -1)) ; outputs
() ; profile action (default)
)
(unit u-media-2-acc "Media-2-acc unit" ()
1 1 ; issue done
() ; state
((ACC40Si INT -1)) ; inputs
((ACC40Sk INT -1)) ; outputs
() ; profile action (default)
)
(unit u-media-2-acc-dual "Media-2-acc-dual unit" ()
1 1 ; issue done
() ; state
((ACC40Si INT -1)) ; inputs
((ACC40Sk INT -1)) ; outputs
() ; profile action (default)
)
(unit u-media-2-add-sub "Media-2-add-sub unit" ()
1 1 ; issue done
() ; state
((ACC40Si INT -1)) ; inputs
((ACC40Sk INT -1)) ; outputs
() ; profile action (default)
)
(unit u-media-2-add-sub-dual "Media-2-add-sub-dual unit" ()
1 1 ; issue done
() ; state
((ACC40Si INT -1)) ; inputs
((ACC40Sk INT -1)) ; outputs
() ; profile action (default)
)
; Media unit M3 -- see table 13-8 in the fr400 LSI
(unit u-media-3 "Media-3 unit" ()
1 1 ; issue done
() ; state
((FRinti INT -1) (FRintj INT -1)) ; inputs
((FRintk INT -1)) ; outputs
() ; profile action (default)
)
(unit u-media-3-dual "Media-3-dual unit" ()
1 1 ; issue done
() ; state
((FRinti INT -1)) ; inputs
((FRintk INT -1)) ; outputs
() ; profile action (default)
)
(unit u-media-3-quad "Media-3-quad unit" ()
1 1 ; issue done
() ; state
((FRinti INT -1) (FRintj INT -1)) ; inputs
((FRintk INT -1)) ; outputs
() ; profile action (default)
)
; Media unit M4 -- see table 13-8 in the fr400 LSI
(unit u-media-4 "Media-4 unit" ()
1 1 ; issue done
() ; state
((ACC40Si INT -1) (FRintj INT -1)) ; inputs
((ACC40Sk INT -1) (FRintk INT -1)) ; outputs
() ; profile action (default)
)
(unit u-media-4-accg "Media-4-accg unit" ()
1 1 ; issue done
() ; state
((ACCGi INT -1) (FRinti INT -1)) ; inputs
((ACCGk INT -1) (FRintk INT -1)) ; outputs
() ; profile action (default)
)
(unit u-media-4-acc-dual "Media-4-acc-dual unit" ()
1 1 ; issue done
() ; state
((ACC40Si INT -1)) ; inputs
((FRintk INT -1)) ; outputs
() ; profile action (default)
)
; Media unit M6 -- see table 13-8 in the fr400 LSI
(unit u-media-6 "Media-6 unit" ()
1 1 ; issue done
() ; state
((FRinti INT -1)) ; inputs
((FRintk INT -1)) ; outputs
() ; profile action (default)
)
; Media unit M7 -- see table 13-8 in the fr400 LSI
(unit u-media-7 "Media-1 unit" ()
1 1 ; issue done
() ; state
((FRinti INT -1) (FRintj INT -1)) ; inputs
((FCCk INT -1)) ; outputs
() ; profile action (default)
)
; Media Dual Expand unit
(unit u-media-dual-expand "Media Dual Expand unit" ()
1 1 ; issue done
() ; state
((FRinti INT -1)) ; inputs
((FRintk INT -1)) ; outputs
() ; profile action (default)
)
; Media Dual half to byte unit
(unit u-media-dual-htob "Media Half to byte" ()
1 1 ; issue done
() ; state
((FRintj INT -1)) ; inputs
((FRintk INT -1)) ; outputs
() ; profile action (default)
)
; Barrier unit
(unit u-barrier "Barrier unit" ()
1 1 ; issue done
() ; state
() ; inputs
() ; outputs
() ; profile action (default)
)
; Memory Barrier unit
(unit u-membar "Memory Barrier unit" ()
1 1 ; issue done
() ; state
() ; inputs
() ; outputs
() ; profile action (default)
)
; Insn cache invalidate unit
(unit u-ici "Insn cache invalidate unit" ()
1 1 ; issue done
() ; state
((GRi INT -1) (GRj INT -1)) ; inputs
() ; outputs
() ; profile action (default)
)
; Data cache invalidate unit
(unit u-dci "Data cache invalidate unit" ()
1 1 ; issue done
() ; state
((GRi INT -1) (GRj INT -1)) ; inputs
() ; outputs
() ; profile action (default)
)
; Data cache flush unit
(unit u-dcf "Data cache flush unit" ()
1 1 ; issue done
() ; state
((GRi INT -1) (GRj INT -1)) ; inputs
() ; outputs
() ; profile action (default)
)
; Insn cache preload unit
(unit u-icpl "Insn cache preload unit" ()
1 1 ; issue done
() ; state
((GRi INT -1) (GRj INT -1)) ; inputs
() ; outputs
() ; profile action (default)
)
; Data cache preload unit
(unit u-dcpl "Data cache preload unit" ()
1 1 ; issue done
() ; state
((GRi INT -1) (GRj INT -1)) ; inputs
() ; outputs
() ; profile action (default)
)
; Insn cache unlock unit
(unit u-icul "Insn cache unlock unit" ()
1 1 ; issue done
() ; state
((GRi INT -1) (GRj INT -1)) ; inputs
() ; outputs
() ; profile action (default)
)
; Data cache unlock unit
(unit u-dcul "Data cache unlock unit" ()
1 1 ; issue done
() ; state
((GRi INT -1) (GRj INT -1)) ; inputs
() ; outputs
() ; profile action (default)
)
)
; FR450 machine
(define-mach
(name fr450)
(comment "FR450 cpu")
(cpu frvbf)
)
(define-model
(name fr450) (comment "FR450 model") (attrs)
(mach fr450)
(pipeline all "" () ((fetch) (decode) (execute) (writeback)))
; `state' is a list of variables for recording model state
(state
; State items
; These are all masks with each bit representing one register.
(prev-fp-load DI) ; Previous use of FR register was floating point load
(prev-fr-p4 DI) ; Previous use of FR register was media unit 4
(prev-fr-p6 DI) ; Previous use of FR register was media unit 6
(prev-acc-p2 DI) ; Previous use of ACC register was media unit 2
(prev-acc-p4 DI) ; Previous use of ACC register was media unit 4
(cur-fp-load DI) ; Current use of FR register is floating point load
(cur-fr-p4 DI) ; Current use of FR register is media unit 4
(cur-fr-p6 DI) ; Current use of FR register is media unit 6
(cur-acc-p2 DI) ; Current use of ACC register is media unit 2
(cur-acc-p4 DI) ; Current use of ACC register is media unit 4
)
(unit u-exec "Execution Unit" ()
1 1 ; issue done
() ; state
() ; inputs
() ; outputs
() ; profile action (default)
)
; Basic integer insn unit
(unit u-integer "Integer Unit" ()
1 1 ; issue done
() ; state
((GRi INT -1) (GRj INT -1)) ; inputs
((GRk INT -1) (ICCi_1 INT -1)) ; outputs
() ; profile action (default)
)
; Integer multiplication unit
(unit u-imul "Integer Multiplication Unit" ()
1 1 ; issue done
() ; state
((GRi INT -1) (GRj INT -1)) ; inputs
((GRdoublek INT -1) (ICCi_1 INT -1)) ; outputs
() ; profile action (default)
)
; Integer division unit
(unit u-idiv "Integer Division Unit" ()
1 1 ; issue done
() ; state
((GRi INT -1) (GRj INT -1)) ; inputs
((GRk INT -1) (ICCi_1 INT -1)) ; outputs
() ; profile action (default)
)
; Branch unit
(unit u-branch "Branch Unit" ()
1 1 ; issue done
() ; state
((GRi INT -1) (GRj INT -1)
(ICCi_2 INT -1) (FCCi_2 INT -1)) ; inputs
((pc)) ; outputs
() ; profile action (default)
)
; Trap unit
(unit u-trap "Trap Unit" ()
1 1 ; issue done
() ; state
((GRi INT -1) (GRj INT -1)
(ICCi_2 INT -1) (FCCi_2 INT -1)) ; inputs
() ; outputs
() ; profile action (default)
)
; Condition code check unit
(unit u-check "Check Unit" ()
1 1 ; issue done
() ; state
((ICCi_3 INT -1) (FCCi_3 INT -1)) ; inputs
() ; outputs
() ; profile action (default)
)
; GR set half unit
(unit u-set-hilo "GR Set Half" ()
1 1 ; issue done
() ; state
() ; inputs
((GRkhi INT -1) (GRklo INT -1)) ; outputs
() ; profile action (default)
)
; GR load unit -- TODO doesn't handle quad
(unit u-gr-load "GR Load Unit" ()
1 1 ; issue done
() ; state
((GRi INT -1) (GRj INT -1)) ; inputs
((GRk INT -1) (GRdoublek INT -1)) ; outputs
() ; profile action (default)
)
; GR store unit -- TODO doesn't handle quad
(unit u-gr-store "GR Store Unit" ()
1 1 ; issue done
() ; state
((GRi INT -1) (GRj INT -1) (GRk INT -1) (GRdoublek INT -1)) ; inputs
() ; outputs
() ; profile action (default)
)
; FR load unit -- TODO doesn't handle quad
(unit u-fr-load "FR Load Unit" ()
1 1 ; issue done
() ; state
((GRi INT -1) (GRj INT -1)) ; inputs
((FRintk INT -1) (FRdoublek INT -1)) ; outputs
() ; profile action (default)
)
; FR store unit -- TODO doesn't handle quad
(unit u-fr-store "FR Store Unit" ()
1 1 ; issue done
() ; state
((GRi INT -1) (GRj INT -1) (FRintk INT -1) (FRdoublek INT -1)) ; inputs
() ; outputs
() ; profile action (default)
)
; Swap unit
(unit u-swap "Swap Unit" ()
1 1 ; issue done
() ; state
((GRi INT -1) (GRj INT -1)) ; inputs
((GRk INT -1)) ; outputs
() ; profile action (default)
)
; FR Move to GR unit
(unit u-fr2gr "FR Move to GR Unit" ()
1 1 ; issue done
() ; state
((FRintk INT -1)) ; inputs
((GRj INT -1)) ; outputs
() ; profile action (default)
)
; SPR Move to GR unit
(unit u-spr2gr "SPR Move to GR Unit" ()
1 1 ; issue done
() ; state
((spr INT -1)) ; inputs
((GRj INT -1)) ; outputs
() ; profile action (default)
)
; GR Move to FR unit
(unit u-gr2fr "GR Move to FR Unit" ()
1 1 ; issue done
() ; state
((GRj INT -1)) ; inputs
((FRintk INT -1)) ; outputs
() ; profile action (default)
)
; GR Move to SPR unit
(unit u-gr2spr "GR Move to SPR Unit" ()
1 1 ; issue done
() ; state
((GRj INT -1)) ; inputs
((spr INT -1)) ; outputs
() ; profile action (default)
)
; Media unit M1 -- see table 14-8 in the fr450 LSI
(unit u-media-1 "Media-1 unit" ()
1 1 ; issue done
() ; state
((FRinti INT -1) (FRintj INT -1)) ; inputs
((FRintk INT -1)) ; outputs
() ; profile action (default)
)
(unit u-media-1-quad "Media-1-quad unit" ()
1 1 ; issue done
() ; state
((FRinti INT -1) (FRintj INT -1)) ; inputs
((FRintk INT -1)) ; outputs
() ; profile action (default)
)
(unit u-media-hilo "Media-hilo unit -- a variation of the Media-1 unit" ()
1 1 ; issue done
() ; state
() ; inputs
((FRkhi INT -1) (FRklo INT -1)) ; outputs
() ; profile action (default)
)
; Media unit M2 -- see table 14-8 in the fr450 LSI
(unit u-media-2 "Media-2 unit" ()
1 1 ; issue done
() ; state
((FRinti INT -1) (FRintj INT -1)) ; inputs
((ACC40Sk INT -1) (ACC40Uk INT -1)) ; outputs
() ; profile action (default)
)
(unit u-media-2-quad "Media-2-quad unit" ()
1 1 ; issue done
() ; state
((FRinti INT -1) (FRintj INT -1)) ; inputs
((ACC40Sk INT -1) (ACC40Uk INT -1)) ; outputs
() ; profile action (default)
)
(unit u-media-2-acc "Media-2-acc unit" ()
1 1 ; issue done
() ; state
((ACC40Si INT -1)) ; inputs
((ACC40Sk INT -1)) ; outputs
() ; profile action (default)
)
(unit u-media-2-acc-dual "Media-2-acc-dual unit" ()
1 1 ; issue done
() ; state
((ACC40Si INT -1)) ; inputs
((ACC40Sk INT -1)) ; outputs
() ; profile action (default)
)
(unit u-media-2-add-sub "Media-2-add-sub unit" ()
1 1 ; issue done
() ; state
((ACC40Si INT -1)) ; inputs
((ACC40Sk INT -1)) ; outputs
() ; profile action (default)
)
(unit u-media-2-add-sub-dual "Media-2-add-sub-dual unit" ()
1 1 ; issue done
() ; state
((ACC40Si INT -1)) ; inputs
((ACC40Sk INT -1)) ; outputs
() ; profile action (default)
)
; Media unit M3 -- see table 14-8 in the fr450 LSI
(unit u-media-3 "Media-3 unit" ()
1 1 ; issue done
() ; state
((FRinti INT -1) (FRintj INT -1)) ; inputs
((FRintk INT -1)) ; outputs
() ; profile action (default)
)
(unit u-media-3-dual "Media-3-dual unit" ()
1 1 ; issue done
() ; state
((FRinti INT -1)) ; inputs
((FRintk INT -1)) ; outputs
() ; profile action (default)
)
(unit u-media-3-quad "Media-3-quad unit" ()
1 1 ; issue done
() ; state
((FRinti INT -1) (FRintj INT -1)) ; inputs
((FRintk INT -1)) ; outputs
() ; profile action (default)
)
; Media unit M4 -- see table 14-8 in the fr450 LSI
(unit u-media-4 "Media-4 unit" ()
1 1 ; issue done
() ; state
((ACC40Si INT -1) (FRintj INT -1)) ; inputs
((ACC40Sk INT -1) (FRintk INT -1)) ; outputs
() ; profile action (default)
)
(unit u-media-4-accg "Media-4-accg unit" ()
1 1 ; issue done
() ; state
((ACCGi INT -1) (FRinti INT -1)) ; inputs
((ACCGk INT -1) (FRintk INT -1)) ; outputs
() ; profile action (default)
)
(unit u-media-4-acc-dual "Media-4-acc-dual unit" ()
1 1 ; issue done
() ; state
((ACC40Si INT -1)) ; inputs
((FRintk INT -1)) ; outputs
() ; profile action (default)
)
(unit u-media-4-mclracca "Media-4 unit for MCLRACC with #A=1" ()
1 1 ; issue done
() ; state
() ; inputs
() ; outputs
() ; profile action (default)
)
; Media unit M6 -- see table 14-8 in the fr450 LSI
(unit u-media-6 "Media-6 unit" ()
1 1 ; issue done
() ; state
((FRinti INT -1)) ; inputs
((FRintk INT -1)) ; outputs
() ; profile action (default)
)
; Media unit M7 -- see table 14-8 in the fr450 LSI
(unit u-media-7 "Media-1 unit" ()
1 1 ; issue done
() ; state
((FRinti INT -1) (FRintj INT -1)) ; inputs
((FCCk INT -1)) ; outputs
() ; profile action (default)
)
; Media Dual Expand unit
(unit u-media-dual-expand "Media Dual Expand unit" ()
1 1 ; issue done
() ; state
((FRinti INT -1)) ; inputs
((FRintk INT -1)) ; outputs
() ; profile action (default)
)
; Media Dual half to byte unit
(unit u-media-dual-htob "Media Half to byte" ()
1 1 ; issue done
() ; state
((FRintj INT -1)) ; inputs
((FRintk INT -1)) ; outputs
() ; profile action (default)
)
; Barrier unit
(unit u-barrier "Barrier unit" ()
1 1 ; issue done
() ; state
() ; inputs
() ; outputs
() ; profile action (default)
)
; Memory Barrier unit
(unit u-membar "Memory Barrier unit" ()
1 1 ; issue done
() ; state
() ; inputs
() ; outputs
() ; profile action (default)
)
; Insn cache invalidate unit
(unit u-ici "Insn cache invalidate unit" ()
1 1 ; issue done
() ; state
((GRi INT -1) (GRj INT -1)) ; inputs
() ; outputs
() ; profile action (default)
)
; Data cache invalidate unit
(unit u-dci "Data cache invalidate unit" ()
1 1 ; issue done
() ; state
((GRi INT -1) (GRj INT -1)) ; inputs
() ; outputs
() ; profile action (default)
)
; Data cache flush unit
(unit u-dcf "Data cache flush unit" ()
1 1 ; issue done
() ; state
((GRi INT -1) (GRj INT -1)) ; inputs
() ; outputs
() ; profile action (default)
)
; Insn cache preload unit
(unit u-icpl "Insn cache preload unit" ()
1 1 ; issue done
() ; state
((GRi INT -1) (GRj INT -1)) ; inputs
() ; outputs
() ; profile action (default)
)
; Data cache preload unit
(unit u-dcpl "Data cache preload unit" ()
1 1 ; issue done
() ; state
((GRi INT -1) (GRj INT -1)) ; inputs
() ; outputs
() ; profile action (default)
)
; Insn cache unlock unit
(unit u-icul "Insn cache unlock unit" ()
1 1 ; issue done
() ; state
((GRi INT -1) (GRj INT -1)) ; inputs
() ; outputs
() ; profile action (default)
)
; Data cache unlock unit
(unit u-dcul "Data cache unlock unit" ()
1 1 ; issue done
() ; state
((GRi INT -1) (GRj INT -1)) ; inputs
() ; outputs
() ; profile action (default)
)
)
; Simple machine - single issue integer machine
(define-mach
(name simple)
(comment "Simple single issue integer cpu")
(cpu frvbf)
)
(define-model
(name simple) (comment "Simple model") (attrs)
(mach simple)
(pipeline all "" () ((fetch) (decode) (execute) (writeback)))
; `state' is a list of variables for recording model state
(state)
(unit u-exec "Execution Unit" ()
1 1 ; issue done
() ; state
() ; inputs
() ; outputs
() ; profile action (default)
)
)
; The instruction fetch/execute cycle.
;
; This is how to fetch and decode an instruction.
; Leave it out for now
; (define-extract (const SI 0))
; This is how to execute a decoded instruction.
; Leave it out for now
; (define-execute (const SI 0))
; An attribute to describe which unit an insn runs in.
(define-attr
(for insn)
(type enum)
(name UNIT)
(comment "parallel execution pipeline selection")
; The order of declaration is significant.
; See the *_unit_mapping tables in frv.opc
; Keep variations on the same unit together.
; Keep the '01' variant immediately after the '1' variant in each unit.
; Keep the 'ALL' variations immediately after the last numbered variant in each unit.
(values NIL
I0 I1 I01 I2 I3 IALL
FM0 FM1 FM01 FM2 FM3 FMALL FMLOW
B0 B1 B01
C
MULT-DIV ; multiply/division slotted differently on different machines
IACC ; iacc multiply slotted differently on different machines
LOAD ; loads slotted differently on different machines
STORE ; store slotted differently on different machines
SCAN ; scan, scani slotted differently on different machines
DCPL ; dcpl slotted differently on different machines
MDUALACC ; media dual acc slotted differently on different machines
MDCUTSSI ; mdcutssi insn slotted differently on different machines
MCLRACC-1; mclracc A==1 slotted differently on different machines
NUM_UNITS
)
)
; Attributes to describe major categories of insns
(define-attr
(for insn)
(type enum)
(name FR400-MAJOR)
(comment "fr400 major insn categories")
; The order of declaration is significant. Keep variations on the same major
; together.
(values NONE
I-1 I-2 I-3 I-4 I-5
B-1 B-2 B-3 B-4 B-5 B-6
C-1 C-2
M-1 M-2
)
)
(define-attr
(for insn)
(type enum)
(name FR450-MAJOR)
(comment "fr450 major insn categories")
; The order of declaration is significant. Keep variations on the same major
; together.
(values NONE
I-1 I-2 I-3 I-4 I-5
B-1 B-2 B-3 B-4 B-5 B-6
C-1 C-2
M-1 M-2 M-3 M-4 M-5 M-6
)
)
(define-attr
(for insn)
(type enum)
(name FR500-MAJOR)
(comment "fr500 major insn categories")
; The order of declaration is significant. Keep variations on the same major
; together.
(values NONE
I-1 I-2 I-3 I-4 I-5 I-6
B-1 B-2 B-3 B-4 B-5 B-6
C-1 C-2
F-1 F-2 F-3 F-4 F-5 F-6 F-7 F-8
M-1 M-2 M-3 M-4 M-5 M-6 M-7 M-8
)
)
(define-attr
(for insn)
(type enum)
(name FR550-MAJOR)
(comment "fr550 major insn categories")
; The order of declaration is significant. Keep variations on the same major
; together.
(values NONE
I-1 I-2 I-3 I-4 I-5 I-6 I-7 I-8
B-1 B-2 B-3 B-4 B-5 B-6
C-1 C-2
F-1 F-2 F-3 F-4
M-1 M-2 M-3 M-4 M-5
)
)
; Privileged insn
(define-attr
(for insn)
(type boolean)
(name PRIVILEGED)
(comment "insn only allowed in supervisor mode")
)
; Non-Excepting insn
(define-attr
(for insn)
(type boolean)
(name NON-EXCEPTING)
(comment "non-excepting insn")
)
; Conditional insn
(define-attr
(for insn)
(type boolean)
(name CONDITIONAL)
(comment "conditional insn")
)
; insn accesses FR registers
(define-attr
(for insn)
(type boolean)
(name FR-ACCESS)
(comment "insn accesses FR registers")
)
; insn preserves MSR.OVF
(define-attr
(for insn)
(type boolean)
(name PRESERVE-OVF)
(comment "Preserve value of MSR.OVF")
)
; "Audio" instruction provided by the fr405 but not the original fr400 core.
(define-attr
(for insn)
(type boolean)
(name AUDIO)
(comment "Audio instruction added with FR405")
)
; null attribute -- used as a place holder for where an attribue is required.
(define-attr
(for insn)
(type boolean)
(name NA)
(comment "placeholder attribute")
(attrs META) ; do not define in any generated file for now
)
; IDOC attribute for instruction documentation.
(define-attr
(for insn)
(type enum)
(name IDOC)
(comment "insn kind for documentation")
(attrs META)
(values
(MEM - () "Memory")
(ALU - () "ALU")
(FPU - () "FPU")
(BR - () "Branch")
(PRIV - () "Priviledged")
(MISC - () "Miscellaneous")
)
)
; Instruction fields.
;
; Attributes:
; PCREL-ADDR: pc relative value (for reloc and disassembly purposes)
; ABS-ADDR: absolute address (for reloc and disassembly purposes?)
; RESERVED: bits are not used to decode insn, must be all 0
(dnf f-pack "packing bit" () 31 1)
(dnf f-op "primary opcode" () 24 7)
(dnf f-ope1 "extended opcode" () 11 6)
(dnf f-ope2 "extended opcode" () 9 4)
(dnf f-ope3 "extended opcode" () 15 3)
(dnf f-ope4 "extended opcode" () 7 2)
(dnf f-GRi "source register 1" () 17 6)
(dnf f-GRj "source register 2" () 5 6)
(dnf f-GRk "destination register" () 30 6)
(dnf f-FRi "source register 1" () 17 6)
(dnf f-FRj "source register 2" () 5 6)
(dnf f-FRk "destination register" () 30 6)
(dnf f-CPRi "source register 1" () 17 6)
(dnf f-CPRj "source register 2" () 5 6)
(dnf f-CPRk "destination register" () 30 6)
(dnf f-ACCGi "source register" () 17 6)
(dnf f-ACCGk "destination register" () 30 6)
(dnf f-ACC40Si "40 bit signed accumulator" () 17 6)
(dnf f-ACC40Ui "40 bit unsigned accumulator" () 17 6)
(dnf f-ACC40Sk "40 bit accumulator" () 30 6)
(dnf f-ACC40Uk "40 bit accumulator" () 30 6)
(dnf f-CRi "source register" () 14 3)
(dnf f-CRj "source register" () 2 3)
(dnf f-CRk "destination register" () 27 3)
(dnf f-CCi "condition register" () 11 3)
(df f-CRj_int "target cr for ck insns" () 26 2 UINT
((value pc) (sub WI value 4))
((value pc) (add WI value 4))
)
(dnf f-CRj_float "target cr for fck insns" () 26 2)
(dnf f-ICCi_1 "condition register" () 11 2)
(dnf f-ICCi_2 "condition register" () 26 2)
(dnf f-ICCi_3 "condition register" () 1 2)
(dnf f-FCCi_1 "condition register" () 11 2)
(dnf f-FCCi_2 "condition register" () 26 2)
(dnf f-FCCi_3 "condition register" () 1 2)
(dnf f-FCCk "condition register" () 26 2)
(dnf f-eir "exception insn register" () 17 6)
(df f-s10 "10 bit sign extended" () 9 10 INT #f #f)
(df f-s12 "12 bit sign extended" () 11 12 INT #f #f)
(df f-d12 "12 bit sign extended" () 11 12 INT #f #f)
(df f-u16 "16 bit unsigned" () 15 16 UINT #f #f)
(df f-s16 "16 bit sign extended" () 15 16 INT #f #f)
(df f-s6 "6 bit signed" () 5 6 INT #f #f)
(df f-s6_1 "6 bit signed" () 11 6 INT #f #f)
(df f-u6 "6 bit unsigned" () 5 6 UINT #f #f)
(df f-s5 "5 bit signed" () 4 5 INT #f #f)
(df f-u12-h "upper 6 bits of u12" () 17 6 INT #f #f)
(df f-u12-l "lower 6 bits of u12" () 5 6 UINT #f #f)
(dnmf f-u12 "12 bit signed immediate" () INT
(f-u12-h f-u12-l)
(sequence () ; insert
(set (ifield f-u12-h) (sra SI (ifield f-u12) 6))
(set (ifield f-u12-l) (and (ifield f-u12) #x3f))
)
(sequence () ; extract
(set (ifield f-u12) (or (mul (ifield f-u12-h) 64)
(ifield f-u12-l)))
)
)
(dnf f-int-cc "integer branch conditions" () 30 4)
(dnf f-flt-cc "floating branch conditions" () 30 4)
(df f-cond "conditional arithmetic" () 8 1 UINT #f #f)
(df f-ccond "lr branch condition" () 12 1 UINT #f #f)
(df f-hint "2 bit branch prediction hint" () 17 2 UINT #f #f)
(df f-LI "link indicator" () 25 1 UINT #f #f)
(df f-lock "cache lock indicator" () 25 1 UINT #f #f)
(df f-debug "debug mode indicator" () 25 1 UINT #f #f)
(df f-A "all accumulator bit" () 17 1 UINT #f #f)
(df f-ae "cache all entries indicator" () 25 1 UINT #f #f)
(dnf f-spr-h "upper 6 bits of spr" () 30 6)
(dnf f-spr-l "lower 6 bits of spr" () 17 6)
(dnmf f-spr "special purpose register" () UINT
(f-spr-h f-spr-l)
(sequence () ; insert
(set (ifield f-spr-h) (srl (ifield f-spr) (const 6)))
(set (ifield f-spr-l) (and (ifield f-spr) (const #x3f)))
)
(sequence () ; extract
(set (ifield f-spr) (or (sll (ifield f-spr-h) (const 6))
(ifield f-spr-l)))
)
)
(df f-label16 "18 bit pc relative signed offset" (PCREL-ADDR) 15 16 INT
((value pc) (sra WI (sub WI value pc) (const 2)))
((value pc) (add WI (mul WI value (const 4)) pc))
)
(df f-labelH6 "upper 6 bits of label24" () 30 6 INT #f #f)
(dnf f-labelL18 "lower 18 bits of label24" () 17 18)
(dnmf f-label24 "26 bit signed offset" (PCREL-ADDR) INT
(f-labelH6 f-labelL18)
; insert
(sequence ()
(set (ifield f-labelH6)
(sra WI (sub (ifield f-label24) pc) (const 20)))
(set (ifield f-labelL18)
(and (srl (sub (ifield f-label24) pc) (const 2))
(const #x3ffff)))
)
; extract
(sequence ()
(set (ifield f-label24)
(add (mul (or (mul (ifield f-labelH6) (sll 1 18))
(ifield f-labelL18))
(const 4))
pc)))
)
(dnf f-LRAE "Load Real Address E flag" () 5 1)
(dnf f-LRAD "Load Real Address D flag" () 4 1)
(dnf f-LRAS "Load Real Address S flag" () 3 1)
(dnf f-TLBPRopx "TLB Probe operation number" () 28 3)
(dnf f-TLBPRL "TLB Probe L flag" () 25 1)
(dnf f-ICCi_1-null "null field" (RESERVED) 11 2)
(dnf f-ICCi_2-null "null field" (RESERVED) 26 2)
(dnf f-ICCi_3-null "null field" (RESERVED) 1 2)
(dnf f-FCCi_1-null "null field" (RESERVED) 11 2)
(dnf f-FCCi_2-null "null field" (RESERVED) 26 2)
(dnf f-FCCi_3-null "null field" (RESERVED) 1 2)
(dnf f-rs-null "null field" (RESERVED) 17 6)
(dnf f-GRi-null "null field" (RESERVED) 17 6)
(dnf f-GRj-null "null field" (RESERVED) 5 6)
(dnf f-GRk-null "null field" (RESERVED) 30 6)
(dnf f-FRi-null "null field" (RESERVED) 17 6)
(dnf f-FRj-null "null field" (RESERVED) 5 6)
(dnf f-ACCj-null "null field" (RESERVED) 5 6)
(dnf f-rd-null "null field" (RESERVED) 30 6)
(dnf f-cond-null "null field" (RESERVED) 30 4)
(dnf f-ccond-null "null field" (RESERVED) 12 1)
(dnf f-s12-null "null field" (RESERVED) 11 12)
(dnf f-label16-null "null field" (RESERVED) 15 16)
(dnf f-misc-null-1 "null field" (RESERVED) 30 5)
(dnf f-misc-null-2 "null field" (RESERVED) 11 6)
(dnf f-misc-null-3 "null field" (RESERVED) 11 4)
(dnf f-misc-null-4 "null field" (RESERVED) 17 2)
(dnf f-misc-null-5 "null field" (RESERVED) 17 16)
(dnf f-misc-null-6 "null field" (RESERVED) 30 3)
(dnf f-misc-null-7 "null field" (RESERVED) 17 3)
(dnf f-misc-null-8 "null field" (RESERVED) 5 3)
(dnf f-misc-null-9 "null field" (RESERVED) 5 4)
(dnf f-misc-null-10 "null field" (RESERVED) 16 5)
(dnf f-misc-null-11 "null field" (RESERVED) 5 1)
(dnf f-LRA-null "null field" (RESERVED) 2 3)
(dnf f-TLBPR-null "null field" (RESERVED) 30 2)
(dnf f-LI-off "null field" (RESERVED) 25 1)
(dnf f-LI-on "null field" (RESERVED) 25 1)
; Relocation annotations.
(dsh h-reloc-ann "relocation annotation" () (register BI))
(dnf f-reloc-ann "relocation annotation" () 0 0)
(define-pmacro (dann xname xcomment xmode xparse xprint)
(define-operand
(name xname)
(comment xcomment)
(type h-reloc-ann)
(index f-reloc-ann)
(mode xmode)
(handlers (parse xparse) (print xprint))
)
)
; Enums.
; insn-op:
; FIXME: should use die macro or some such
(define-normal-insn-enum insn-op "insn op enums" () OP_ f-op
(
"00" "01" "02" "03" "04" "05" "06" "07" "08" "09" "0A" "0B" "0C" "0D" "0E" "0F"
"10" "11" "12" "13" "14" "15" "16" "17" "18" "19" "1A" "1B" "1C" "1D" "1E" "1F"
"20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "2A" "2B" "2C" "2D" "2E" "2F"
"30" "31" "32" "33" "34" "35" "36" "37" "38" "39" "3A" "3B" "3C" "3D" "3E" "3F"
"40" "41" "42" "43" "44" "45" "46" "47" "48" "49" "4A" "4B" "4C" "4D" "4E" "4F"
"50" "51" "52" "53" "54" "55" "56" "57" "58" "59" "5A" "5B" "5C" "5D" "5E" "5F"
"60" "61" "62" "63" "64" "65" "66" "67" "68" "69" "6A" "6B" "6C" "6D" "6E" "6F"
"70" "71" "72" "73" "74" "75" "76" "77" "78" "79" "7A" "7B" "7C" "7D" "7E" "7F"
)
)
(define-normal-insn-enum insn-ope1 "insn ope enums" () OPE1_ f-ope1
(
"00" "01" "02" "03" "04" "05" "06" "07" "08" "09" "0A" "0B" "0C" "0D" "0E" "0F"
"10" "11" "12" "13" "14" "15" "16" "17" "18" "19" "1A" "1B" "1C" "1D" "1E" "1F"
"20" "21" "22" "23" "24" "25" "26" "27" "28" "29" "2A" "2B" "2C" "2D" "2E" "2F"
"30" "31" "32" "33" "34" "35" "36" "37" "38" "39" "3A" "3B" "3C" "3D" "3E" "3F"
)
)
(define-normal-insn-enum insn-ope2 "insn ope enums" () OPE2_ f-ope2
(
"00" "01" "02" "03" "04" "05" "06" "07" "08" "09" "0A" "0B" "0C" "0D" "0E" "0F"
)
)
(define-normal-insn-enum insn-ope3 "insn ope enums" () OPE3_ f-ope3
(
"00" "01" "02" "03" "04" "05" "06" "07"
)
)
(define-normal-insn-enum insn-ope4 "insn ope enums" () OPE4_ f-ope4
(
"0" "1" "2" "3"
)
)
; int-cc: integer branch conditions
; FIXME: should use die macro or some such
(define-normal-insn-enum int-cc "integer branch cond enums" () ICC_ f-int-cc
(
"nev" "c" "v" "lt" "eq" "ls" "n" "le"
"ra" "nc" "nv" "ge" "ne" "hi" "p" "gt"
)
)
; flt-cc: floating-point/media branch conditions
; FIXME: should use die macro or some such
(define-normal-insn-enum flt-cc "float branch cond enums" () FCC_ f-flt-cc
("nev" "u" "gt" "ug" "lt" "ul" "lg" "ne"
"eq" "ue" "ge" "uge" "le" "ule" "o" "ra")
)
; Hardware pieces.
; These entries list the elements of the raw hardware.
; They're also used to provide tables and other elements of the assembly
; language.
(dnh h-pc "program counter" (PC PROFILE) (pc) () () ())
; The PSR. The individual fields are referenced more than the entire
; register, so reference them directly. We can assemble the
; entire register contents when necessary.
;
(dsh h-psr_imple "PSR.IMPLE" () (register UQI))
(dsh h-psr_ver "PSR.VER" () (register UQI))
(dsh h-psr_ice "PSR.ICE bit" () (register BI))
(dsh h-psr_nem "PSR.NEM bit" () (register BI))
(dsh h-psr_cm "PSR.CM bit" () (register BI))
(dsh h-psr_be "PSR.BE bit" () (register BI))
(dsh h-psr_esr "PSR.ESR bit" () (register BI))
(dsh h-psr_ef "PSR.EF bit" () (register BI))
(dsh h-psr_em "PSR.EM bit" () (register BI))
(dsh h-psr_pil "PSR.PIL " () (register UQI))
(dsh h-psr_ps "PSR.PS bit" () (register BI))
(dsh h-psr_et "PSR.ET bit" () (register BI))
; PSR.S requires special handling because the shadow registers (SR0-SR4) must
; be switched with GR4-GR7 when changing from user to supervisor mode or
; vice-versa.
(define-hardware
(name h-psr_s)
(comment "PSR.S bit")
(attrs)
(type register BI)
(get)
(set (newval) (c-call VOID "@cpu@_h_psr_s_set_handler" newval))
)
; The TBR. The individual bits are referenced more than the entire
; register, so reference them directly. We can assemble the
; entire register contents when necessary.
;
(dsh h-tbr_tba "TBR.TBA" () (register UWI))
(dsh h-tbr_tt "TBR.TT" () (register UQI))
; The BPSR. The individual bits are referenced more than the entire
; register, so reference them directly. We can assemble the
; entire register contents when necessary.
;
(dsh h-bpsr_bs "PSR.S bit" () (register BI))
(dsh h-bpsr_bet "PSR.ET bit" () (register BI))
; General registers
;
(define-keyword
(name gr-names)
(print-name h-gr)
(prefix "")
(values
(sp 1) (fp 2)
(gr0 0)(gr1 1)(gr2 2)(gr3 3)(gr4 4)(gr5 5)(gr6 6)(gr7 7)
(gr8 8)(gr9 9)(gr10 10)(gr11 11)(gr12 12)(gr13 13)(gr14 14)(gr15 15)
(gr16 16)(gr17 17)(gr18 18)(gr19 19)(gr20 20)(gr21 21)(gr22 22)(gr23 23)
(gr24 24)(gr25 25)(gr26 26)(gr27 27)(gr28 28)(gr29 29)(gr30 30)(gr31 31)
(gr32 32)(gr33 33)(gr34 34)(gr35 35)(gr36 36)(gr37 37)(gr38 38)(gr39 39)
(gr40 40)(gr41 41)(gr42 42)(gr43 43)(gr44 44)(gr45 45)(gr46 46)(gr47 47)
(gr48 48)(gr49 49)(gr50 50)(gr51 51)(gr52 52)(gr53 53)(gr54 54)(gr55 55)
(gr56 56)(gr57 57)(gr58 58)(gr59 59)(gr60 60)(gr61 61)(gr62 62)(gr63 63)
)
)
(define-hardware
(name h-gr)
(comment "general registers")
(attrs PROFILE)
(type register USI (64))
(indices extern-keyword gr-names)
(get (index) (c-call WI "@cpu@_h_gr_get_handler" index))
(set (index newval) (c-call VOID "@cpu@_h_gr_set_handler" index newval))
)
; General Registers as double words
; These registers are shadowed onto h-gr
(define-hardware
(name h-gr_double)
(comment "general registers as double words")
(attrs PROFILE VIRTUAL)
(type register DI (32))
; FIXME: Need constraint to prohibit odd numbers.
(indices extern-keyword gr-names)
(get (index)
(c-call DI "@cpu@_h_gr_double_get_handler" index))
(set (index newval)
(c-call VOID "@cpu@_h_gr_double_set_handler" index newval))
)
; General Registers as high and low half words
; These registers are shadowed onto h-gr
(define-hardware
(name h-gr_hi)
(comment "general registers as high half word")
(attrs PROFILE VIRTUAL)
(type register UHI (64))
(indices extern-keyword gr-names)
(get (index) (c-call UHI "@cpu@_h_gr_hi_get_handler" index))
(set (index newval) (c-call VOID "@cpu@_h_gr_hi_set_handler" index newval))
)
(define-hardware
(name h-gr_lo)
(comment "general registers as low half word")
(attrs PROFILE VIRTUAL)
(type register UHI (64))
(indices extern-keyword gr-names)
(get (index) (c-call UHI "@cpu@_h_gr_lo_get_handler" index))
(set (index newval) (c-call VOID "@cpu@_h_gr_lo_set_handler" index newval))
)
; Floating Point Registers
(define-keyword
(name fr-names)
(print-name h-fr)
(prefix "")
(values
(fr0 0)(fr1 1)(fr2 2)(fr3 3)(fr4 4)(fr5 5)(fr6 6)(fr7 7)
(fr8 8)(fr9 9)(fr10 10)(fr11 11)(fr12 12)(fr13 13)(fr14 14)(fr15 15)
(fr16 16)(fr17 17)(fr18 18)(fr19 19)(fr20 20)(fr21 21)(fr22 22)(fr23 23)
(fr24 24)(fr25 25)(fr26 26)(fr27 27)(fr28 28)(fr29 29)(fr30 30)(fr31 31)
(fr32 32)(fr33 33)(fr34 34)(fr35 35)(fr36 36)(fr37 37)(fr38 38)(fr39 39)
(fr40 40)(fr41 41)(fr42 42)(fr43 43)(fr44 44)(fr45 45)(fr46 46)(fr47 47)
(fr48 48)(fr49 49)(fr50 50)(fr51 51)(fr52 52)(fr53 53)(fr54 54)(fr55 55)
(fr56 56)(fr57 57)(fr58 58)(fr59 59)(fr60 60)(fr61 61)(fr62 62)(fr63 63)
)
)
(define-hardware
(name h-fr)
(comment "floating point registers")
(attrs PROFILE)
(type register SF (64))
(indices extern-keyword fr-names)
(get (index) (c-call SF "@cpu@_h_fr_get_handler" index))
(set (index newval) (c-call VOID "@cpu@_h_fr_set_handler" index newval))
)
; Floating Point Registers as double precision
; These registers are shadowed onto h-fr
(define-hardware
(name h-fr_double)
(comment "floating point registers as double precision")
(attrs PROFILE VIRTUAL)
(type register DF (32))
; FIXME: Need constraint to prohibit odd numbers.
(indices extern-keyword fr-names)
(get (index)
(c-call DF "@cpu@_h_fr_double_get_handler" index))
(set (index newval)
(c-call VOID "@cpu@_h_fr_double_set_handler" index newval))
)
; Floating Point Registers as integer words.
; These registers are shadowed onto h-fr
(define-hardware
(name h-fr_int)
(comment "floating point registers as integers")
(attrs PROFILE VIRTUAL)
(type register USI (64))
(indices extern-keyword fr-names)
(get (index)
(c-call USI "@cpu@_h_fr_int_get_handler" index))
(set (index newval)
(c-call VOID "@cpu@_h_fr_int_set_handler" index newval))
)
; Floating Point Registers as high and low half words
; These registers are shadowed onto h-fr
(define-hardware
(name h-fr_hi)
(comment "floating point registers as unsigned high half word")
(attrs PROFILE VIRTUAL)
(type register UHI (64))
(indices extern-keyword fr-names)
(get (regno) (srl (reg h-fr_int regno) 16))
(set (regno newval) (set (reg h-fr_int regno)
(or (and (reg h-fr_int regno) #xffff)
(sll newval 16))))
)
(define-hardware
(name h-fr_lo)
(comment "floating point registers as unsigned low half word")
(attrs PROFILE VIRTUAL)
(type register UHI (64))
(indices extern-keyword fr-names)
(get (regno) (and (reg h-fr_int regno) #xffff))
(set (regno newval) (set (reg h-fr_int regno)
(or (and (reg h-fr_int regno) #xffff0000)
(and newval #xffff))))
)
; Floating Point Registers as unsigned bytes
; These registers are shadowed onto h-fr
(define-hardware
(name h-fr_0)
(comment "floating point registers as unsigned byte 0")
(attrs PROFILE VIRTUAL)
(type register UHI (64))
(indices extern-keyword fr-names)
(get (regno) (and (reg h-fr_int regno) #xff))
(set (regno newval)
(sequence ()
(if (gt USI newval #xff)
(set newval #xff))
(set (reg h-fr_int regno) (or (and (reg h-fr_int regno) #xffffff00)
newval))))
)
(define-hardware
(name h-fr_1)
(comment "floating point registers as unsigned byte 1")
(attrs PROFILE VIRTUAL)
(type register UHI (64))
(indices extern-keyword fr-names)
(get (regno) (and (srl (reg h-fr_int regno) 8) #xff))
(set (regno newval)
(sequence ()
(if (gt USI newval #xff)
(set newval #xff))
(set (reg h-fr_int regno) (or (and (reg h-fr_int regno) #xffff00ff)
(sll newval 8)))))
)
(define-hardware
(name h-fr_2)
(comment "floating point registers as unsigned byte 2")
(attrs PROFILE VIRTUAL)
(type register UHI (64))
(indices extern-keyword fr-names)
(get (regno) (and (srl (reg h-fr_int regno) 16) #xff))
(set (regno newval)
(sequence ()
(if (gt USI newval #xff)
(set newval #xff))
(set (reg h-fr_int regno) (or (and (reg h-fr_int regno) #xff00ffff)
(sll newval 16)))))
)
(define-hardware
(name h-fr_3)
(comment "floating point registers as unsigned byte 3")
(attrs PROFILE VIRTUAL)
(type register UHI (64))
(indices extern-keyword fr-names)
(get (regno) (and (srl (reg h-fr_int regno) 24) #xff))
(set (regno newval)
(sequence ()
(if (gt USI newval #xff)
(set newval #xff))
(set (reg h-fr_int regno) (or (and (reg h-fr_int regno) #x00ffffff)
(sll newval 24)))))
)
; Coprocessor Registers
;
(define-keyword
(name cpr-names)
(print-name h-cpr)
(prefix "")
(values
(cpr0 0)(cpr1 1)(cpr2 2)(cpr3 3)(cpr4 4)(cpr5 5)(cpr6 6)(cpr7 7)
(cpr8 8)(cpr9 9)(cpr10 10)(cpr11 11)(cpr12 12)(cpr13 13)(cpr14 14)(cpr15 15)
(cpr16 16)(cpr17 17)(cpr18 18)(cpr19 19)(cpr20 20)(cpr21 21)(cpr22 22)(cpr23 23)
(cpr24 24)(cpr25 25)(cpr26 26)(cpr27 27)(cpr28 28)(cpr29 29)(cpr30 30)(cpr31 31)
(cpr32 32)(cpr33 33)(cpr34 34)(cpr35 35)(cpr36 36)(cpr37 37)(cpr38 38)(cpr39 39)
(cpr40 40)(cpr41 41)(cpr42 42)(cpr43 43)(cpr44 44)(cpr45 45)(cpr46 46)(cpr47 47)
(cpr48 48)(cpr49 49)(cpr50 50)(cpr51 51)(cpr52 52)(cpr53 53)(cpr54 54)(cpr55 55)
(cpr56 56)(cpr57 57)(cpr58 58)(cpr59 59)(cpr60 60)(cpr61 61)(cpr62 62)(cpr63 63)
)
)
(define-hardware
(name h-cpr)
(comment "coprocessor registers")
(attrs PROFILE (MACH frv))
(type register WI (64))
(indices extern-keyword cpr-names)
)
; Coprocessor Registers as double words
; These registers are shadowed onto h-cpr
(define-hardware
(name h-cpr_double)
(comment "coprocessor registers as double words")
(attrs PROFILE VIRTUAL (MACH frv))
(type register DI (32))
; FIXME: Need constraint to prohibit odd numbers.
(indices extern-keyword cpr-names)
(get (index)
(c-call DI "@cpu@_h_cpr_double_get_handler" index))
(set (index newval)
(c-call VOID "@cpu@_h_cpr_double_set_handler" index newval))
)
; Special Purpose Registers
;
(define-keyword
(name spr-names)
(print-name h-spr)
(prefix "")
(values
(psr 0) (pcsr 1) (bpcsr 2) (tbr 3) (bpsr 4)
(hsr0 16) (hsr1 17) (hsr2 18) (hsr3 19)
(hsr4 20) (hsr5 21) (hsr6 22) (hsr7 23)
(hsr8 24) (hsr9 25) (hsr10 26) (hsr11 27)
(hsr12 28) (hsr13 29) (hsr14 30) (hsr15 31)
(hsr16 32) (hsr17 33) (hsr18 34) (hsr19 35)
(hsr20 36) (hsr21 37) (hsr22 38) (hsr23 39)
(hsr24 40) (hsr25 41) (hsr26 42) (hsr27 43)
(hsr28 44) (hsr29 45) (hsr30 46) (hsr31 47)
(hsr32 48) (hsr33 49) (hsr34 50) (hsr35 51)
(hsr36 52) (hsr37 53) (hsr38 54) (hsr39 55)
(hsr40 56) (hsr41 57) (hsr42 58) (hsr43 59)
(hsr44 60) (hsr45 61) (hsr46 62) (hsr47 63)
(hsr48 64) (hsr49 65) (hsr50 66) (hsr51 67)
(hsr52 68) (hsr53 69) (hsr54 70) (hsr55 71)
(hsr56 72) (hsr57 73) (hsr58 74) (hsr59 75)
(hsr60 76) (hsr61 77) (hsr62 78) (hsr63 79)
(ccr 256) (cccr 263) (lr 272) (lcr 273) (iacc0h 280) (iacc0l 281) (isr 288)
(neear0 352) (neear1 353) (neear2 354) (neear3 355)
(neear4 356) (neear5 357) (neear6 358) (neear7 359)
(neear8 360) (neear9 361) (neear10 362) (neear11 363)
(neear12 364) (neear13 365) (neear14 366) (neear15 367)
(neear16 368) (neear17 369) (neear18 370) (neear19 371)
(neear20 372) (neear21 373) (neear22 374) (neear23 375)
(neear24 376) (neear25 377) (neear26 378) (neear27 379)
(neear28 380) (neear29 381) (neear30 382) (neear31 383)
(nesr0 384) (nesr1 385) (nesr2 386) (nesr3 387)
(nesr4 388) (nesr5 389) (nesr6 390) (nesr7 391)
(nesr8 392) (nesr9 393) (nesr10 394) (nesr11 395)
(nesr12 396) (nesr13 397) (nesr14 398) (nesr15 399)
(nesr16 400) (nesr17 401) (nesr18 402) (nesr19 403)
(nesr20 404) (nesr21 405) (nesr22 406) (nesr23 407)
(nesr24 408) (nesr25 409) (nesr26 410) (nesr27 411)
(nesr28 412) (nesr29 413) (nesr30 414) (nesr31 415)
(necr 416)
(gner0 432) (gner1 433)
(fner0 434) (fner1 435)
(epcr0 512) (epcr1 513) (epcr2 514) (epcr3 515)
(epcr4 516) (epcr5 517) (epcr6 518) (epcr7 519)
(epcr8 520) (epcr9 521) (epcr10 522) (epcr11 523)
(epcr12 524) (epcr13 525) (epcr14 526) (epcr15 527)
(epcr16 528) (epcr17 529) (epcr18 530) (epcr19 531)
(epcr20 532) (epcr21 533) (epcr22 534) (epcr23 535)
(epcr24 536) (epcr25 537) (epcr26 538) (epcr27 539)
(epcr28 540) (epcr29 541) (epcr30 542) (epcr31 543)
(epcr32 544) (epcr33 545) (epcr34 546) (epcr35 547)
(epcr36 548) (epcr37 549) (epcr38 550) (epcr39 551)
(epcr40 552) (epcr41 553) (epcr42 554) (epcr43 555)
(epcr44 556) (epcr45 557) (epcr46 558) (epcr47 559)
(epcr48 560) (epcr49 561) (epcr50 562) (epcr51 563)
(epcr52 564) (epcr53 565) (epcr54 566) (epcr55 567)
(epcr56 568) (epcr57 569) (epcr58 570) (epcr59 571)
(epcr60 572) (epcr61 573) (epcr62 574) (epcr63 575)
(esr0 576) (esr1 577) (esr2 578) (esr3 579)
(esr4 580) (esr5 581) (esr6 582) (esr7 583)
(esr8 584) (esr9 585) (esr10 586) (esr11 587)
(esr12 588) (esr13 589) (esr14 590) (esr15 591)
(esr16 592) (esr17 593) (esr18 594) (esr19 595)
(esr20 596) (esr21 597) (esr22 598) (esr23 599)
(esr24 600) (esr25 601) (esr26 602) (esr27 603)
(esr28 604) (esr29 605) (esr30 606) (esr31 607)
(esr32 608) (esr33 609) (esr34 610) (esr35 611)
(esr36 612) (esr37 613) (esr38 614) (esr39 615)
(esr40 616) (esr41 617) (esr42 618) (esr43 619)
(esr44 620) (esr45 621) (esr46 622) (esr47 623)
(esr48 624) (esr49 625) (esr50 626) (esr51 627)
(esr52 628) (esr53 629) (esr54 630) (esr55 631)
(esr56 632) (esr57 633) (esr58 634) (esr59 635)
(esr60 636) (esr61 637) (esr62 638) (esr63 639)
(eir0 640) (eir1 641) (eir2 642) (eir3 643)
(eir4 644) (eir5 645) (eir6 646) (eir7 647)
(eir8 648) (eir9 649) (eir10 650) (eir11 651)
(eir12 652) (eir13 653) (eir14 654) (eir15 655)
(eir16 656) (eir17 657) (eir18 658) (eir19 659)
(eir20 660) (eir21 661) (eir22 662) (eir23 663)
(eir24 664) (eir25 665) (eir26 666) (eir27 667)
(eir28 668) (eir29 669) (eir30 670) (eir31 671)
(esfr0 672) (esfr1 673)
(sr0 768) (sr1 769) (sr2 770) (sr3 771)
(scr0 832) (scr1 833) (scr2 834) (scr3 835)
(fsr0 1024) (fsr1 1025) (fsr2 1026) (fsr3 1027)
(fsr4 1028) (fsr5 1029) (fsr6 1030) (fsr7 1031)
(fsr8 1032) (fsr9 1033) (fsr10 1034) (fsr11 1035)
(fsr12 1036) (fsr13 1037) (fsr14 1038) (fsr15 1039)
(fsr16 1040) (fsr17 1041) (fsr18 1042) (fsr19 1043)
(fsr20 1044) (fsr21 1045) (fsr22 1046) (fsr23 1047)
(fsr24 1048) (fsr25 1049) (fsr26 1050) (fsr27 1051)
(fsr28 1052) (fsr29 1053) (fsr30 1054) (fsr31 1055)
(fsr32 1056) (fsr33 1057) (fsr34 1058) (fsr35 1059)
(fsr36 1060) (fsr37 1061) (fsr38 1062) (fsr39 1063)
(fsr40 1064) (fsr41 1065) (fsr42 1066) (fsr43 1067)
(fsr44 1068) (fsr45 1069) (fsr46 1070) (fsr47 1071)
(fsr48 1072) (fsr49 1073) (fsr50 1074) (fsr51 1075)
(fsr52 1076) (fsr53 1077) (fsr54 1078) (fsr55 1079)
(fsr56 1080) (fsr57 1081) (fsr58 1082) (fsr59 1083)
(fsr60 1084) (fsr61 1085) (fsr62 1086) (fsr63 1087)
; FQ0-FQ31 are 64 bit registers.
; These names allow access to the upper 32 bits of the FQ registers.
(fqop0 1088) (fqop1 1090) (fqop2 1092) (fqop3 1094)
(fqop4 1096) (fqop5 1098) (fqop6 1100) (fqop7 1102)
(fqop8 1104) (fqop9 1106) (fqop10 1108) (fqop11 1110)
(fqop12 1112) (fqop13 1114) (fqop14 1116) (fqop15 1118)
(fqop16 1120) (fqop17 1122) (fqop18 1124) (fqop19 1126)
(fqop20 1128) (fqop21 1130) (fqop22 1132) (fqop23 1134)
(fqop24 1136) (fqop25 1138) (fqop26 1140) (fqop27 1142)
(fqop28 1144) (fqop29 1146) (fqop30 1148) (fqop31 1150)
; These names allow access to the lower 32 bits of the FQ registers.
(fqst0 1089) (fqst1 1091) (fqst2 1093) (fqst3 1095)
(fqst4 1097) (fqst5 1099) (fqst6 1101) (fqst7 1103)
(fqst8 1105) (fqst9 1107) (fqst10 1109) (fqst11 1111)
(fqst12 1113) (fqst13 1115) (fqst14 1117) (fqst15 1119)
(fqst16 1121) (fqst17 1123) (fqst18 1125) (fqst19 1127)
(fqst20 1129) (fqst21 1131) (fqst22 1133) (fqst23 1135)
(fqst24 1137) (fqst25 1139) (fqst26 1141) (fqst27 1143)
(fqst28 1145) (fqst29 1147) (fqst30 1149) (fqst31 1151)
; These also access the lower 32 bits of the FQ registers.
; These are not accessible as spr registers (see LSI appendix - section 13.4)
; (fq0 1089) (fq1 1091) (fq2 1093) (fq3 1095)
; (fq4 1097) (fq5 1099) (fq6 1101) (fq7 1103)
; (fq8 1105) (fq9 1107) (fq10 1109) (fq11 1111)
; (fq12 1113) (fq13 1115) (fq14 1117) (fq15 1119)
; (fq16 1121) (fq17 1123) (fq18 1125) (fq19 1127)
; (fq20 1129) (fq21 1131) (fq22 1133) (fq23 1135)
; (fq24 1137) (fq25 1139) (fq26 1141) (fq27 1143)
; (fq28 1145) (fq29 1147) (fq30 1149) (fq31 1151)
(mcilr0 1272) (mcilr1 1273)
(msr0 1280) (msr1 1281) (msr2 1282) (msr3 1283)
(msr4 1284) (msr5 1285) (msr6 1286) (msr7 1287)
(msr8 1288) (msr9 1289) (msr10 1290) (msr11 1291)
(msr12 1292) (msr13 1293) (msr14 1294) (msr15 1295)
(msr16 1296) (msr17 1297) (msr18 1298) (msr19 1299)
(msr20 1300) (msr21 1301) (msr22 1302) (msr23 1303)
(msr24 1304) (msr25 1305) (msr26 1306) (msr27 1307)
(msr28 1308) (msr29 1309) (msr30 1310) (msr31 1311)
(msr32 1312) (msr33 1313) (msr34 1314) (msr35 1315)
(msr36 1316) (msr37 1317) (msr38 1318) (msr39 1319)
(msr40 1320) (msr41 1321) (msr42 1322) (msr43 1323)
(msr44 1324) (msr45 1325) (msr46 1326) (msr47 1327)
(msr48 1328) (msr49 1329) (msr50 1330) (msr51 1331)
(msr52 1332) (msr53 1333) (msr54 1334) (msr55 1335)
(msr56 1336) (msr57 1337) (msr58 1338) (msr59 1339)
(msr60 1340) (msr61 1341) (msr62 1342) (msr63 1343)
; MQ0-MQ31 are 64 bit registers.
; These names allow access to the upper 32 bits of the MQ registers.
(mqop0 1344) (mqop1 1346) (mqop2 1348) (mqop3 1350)
(mqop4 1352) (mqop5 1354) (mqop6 1356) (mqop7 1358)
(mqop8 1360) (mqop9 1362) (mqop10 1364) (mqop11 1366)
(mqop12 1368) (mqop13 1370) (mqop14 1372) (mqop15 1374)
(mqop16 1376) (mqop17 1378) (mqop18 1380) (mqop19 1382)
(mqop20 1384) (mqop21 1386) (mqop22 1388) (mqop23 1390)
(mqop24 1392) (mqop25 1394) (mqop26 1396) (mqop27 1398)
(mqop28 1400) (mqop29 1402) (mqop30 1404) (mqop31 1406)
; These names allow access to the lower 32 bits of the MQ registers.
(mqst0 1345) (mqst1 1347) (mqst2 1349) (mqst3 1351)
(mqst4 1353) (mqst5 1355) (mqst6 1357) (mqst7 1359)
(mqst8 1361) (mqst9 1363) (mqst10 1365) (mqst11 1367)
(mqst12 1369) (mqst13 1371) (mqst14 1373) (mqst15 1375)
(mqst16 1377) (mqst17 1379) (mqst18 1381) (mqst19 1383)
(mqst20 1385) (mqst21 1387) (mqst22 1389) (mqst23 1391)
(mqst24 1393) (mqst25 1395) (mqst26 1397) (mqst27 1399)
(mqst28 1401) (mqst29 1403) (mqst30 1405) (mqst31 1407)
; These also access the lower 32 bits of the MQ registers.
; These are not accessible as spr registers (see LSI appendix - section 13.4)
; (mq0 1345) (mq1 1347) (mq2 1349) (mq3 1351)
; (mq4 1353) (mq5 1355) (mq6 1357) (mq7 1359)
; (mq8 1361) (mq9 1363) (mq10 1365) (mq11 1367)
; (mq12 1369) (mq13 1371) (mq14 1373) (mq15 1375)
; (mq16 1377) (mq17 1379) (mq18 1381) (mq19 1383)
; (mq20 1385) (mq21 1387) (mq22 1389) (mq23 1391)
; (mq24 1393) (mq25 1395) (mq26 1397) (mq27 1399)
; (mq28 1401) (mq29 1403) (mq30 1405) (mq31 1407)
; These are not accessible as spr registers (see LSI appendix - section 13.4)
; (acc0 1408) (acc1 1409) (acc2 1410) (acc3 1411)
; (acc4 1412) (acc5 1413) (acc6 1414) (acc7 1415)
; (acc8 1416) (acc9 1417) (acc10 1418) (acc11 1419)
; (acc12 1420) (acc13 1421) (acc14 1422) (acc15 1423)
; (acc16 1424) (acc17 1425) (acc18 1426) (acc19 1427)
; (acc20 1428) (acc21 1429) (acc22 1430) (acc23 1431)
; (acc24 1432) (acc25 1433) (acc26 1434) (acc27 1435)
; (acc28 1436) (acc29 1437) (acc30 1438) (acc31 1439)
; (acc32 1440) (acc33 1441) (acc34 1442) (acc35 1443)
; (acc36 1444) (acc37 1445) (acc38 1446) (acc39 1447)
; (acc40 1448) (acc41 1449) (acc42 1450) (acc43 1451)
; (acc44 1452) (acc45 1453) (acc46 1454) (acc47 1455)
; (acc48 1456) (acc49 1457) (acc50 1458) (acc51 1459)
; (acc52 1460) (acc53 1461) (acc54 1462) (acc55 1463)
; (acc56 1464) (acc57 1465) (acc58 1466) (acc59 1467)
; (acc60 1468) (acc61 1469) (acc62 1470) (acc63 1471)
; (accg0 1472) (accg1 1473) (accg2 1474) (accg3 1475)
; (accg4 1476) (accg5 1477) (accg6 1478) (accg7 1479)
; (accg8 1480) (accg9 1481) (accg10 1482) (accg11 1483)
; (accg12 1484) (accg13 1485) (accg14 1486) (accg15 1487)
; (accg16 1488) (accg17 1489) (accg18 1490) (accg19 1491)
; (accg20 1492) (accg21 1493) (accg22 1494) (accg23 1495)
; (accg24 1496) (accg25 1497) (accg26 1498) (accg27 1499)
; (accg28 1500) (accg29 1501) (accg30 1502) (accg31 1503)
; (accg32 1504) (accg33 1505) (accg34 1506) (accg35 1507)
; (accg36 1508) (accg37 1509) (accg38 1510) (accg39 1511)
; (accg40 1512) (accg41 1513) (accg42 1514) (accg43 1515)
; (accg44 1516) (accg45 1517) (accg46 1518) (accg47 1519)
; (accg48 1520) (accg49 1521) (accg50 1522) (accg51 1523)
; (accg52 1524) (accg53 1525) (accg54 1526) (accg55 1527)
; (accg56 1528) (accg57 1529) (accg58 1530) (accg59 1531)
; (accg60 1532) (accg61 1533) (accg62 1534) (accg63 1535)
(ear0 1536) (ear1 1537) (ear2 1538) (ear3 1539)
(ear4 1540) (ear5 1541) (ear6 1542) (ear7 1543)
(ear8 1544) (ear9 1545) (ear10 1546) (ear11 1547)
(ear12 1548) (ear13 1549) (ear14 1550) (ear15 1551)
(ear16 1552) (ear17 1553) (ear18 1554) (ear19 1555)
(ear20 1556) (ear21 1557) (ear22 1558) (ear23 1559)
(ear24 1560) (ear25 1561) (ear26 1562) (ear27 1563)
(ear28 1564) (ear29 1565) (ear30 1566) (ear31 1567)
(ear32 1568) (ear33 1569) (ear34 1570) (ear35 1571)
(ear36 1572) (ear37 1573) (ear38 1574) (ear39 1575)
(ear40 1576) (ear41 1577) (ear42 1578) (ear43 1579)
(ear44 1580) (ear45 1581) (ear46 1582) (ear47 1583)
(ear48 1584) (ear49 1585) (ear50 1586) (ear51 1587)
(ear52 1588) (ear53 1589) (ear54 1590) (ear55 1591)
(ear56 1592) (ear57 1593) (ear58 1594) (ear59 1595)
(ear60 1596) (ear61 1597) (ear62 1598) (ear63 1599)
(edr0 1600) (edr1 1601) (edr2 1602) (edr3 1603)
(edr4 1604) (edr5 1605) (edr6 1606) (edr7 1607)
(edr8 1608) (edr9 1609) (edr10 1610) (edr11 1611)
(edr12 1612) (edr13 1613) (edr14 1614) (edr15 1615)
(edr16 1616) (edr17 1617) (edr18 1618) (edr19 1619)
(edr20 1620) (edr21 1621) (edr22 1622) (edr23 1623)
(edr24 1624) (edr25 1625) (edr26 1626) (edr27 1627)
(edr28 1628) (edr29 1629) (edr30 1630) (edr31 1631)
(edr32 1632) (edr33 1636) (edr34 1634) (edr35 1635)
(edr36 1636) (edr37 1637) (edr38 1638) (edr39 1639)
(edr40 1640) (edr41 1641) (edr42 1642) (edr43 1643)
(edr44 1644) (edr45 1645) (edr46 1646) (edr47 1647)
(edr48 1648) (edr49 1649) (edr50 1650) (edr51 1651)
(edr52 1652) (edr53 1653) (edr54 1654) (edr55 1655)
(edr56 1656) (edr57 1657) (edr58 1658) (edr59 1659)
(edr60 1660) (edr61 1661) (edr62 1662) (edr63 1663)
(iamlr0 1664) (iamlr1 1665) (iamlr2 1666) (iamlr3 1667)
(iamlr4 1668) (iamlr5 1669) (iamlr6 1670) (iamlr7 1671)
(iamlr8 1672) (iamlr9 1673) (iamlr10 1674) (iamlr11 1675)
(iamlr12 1676) (iamlr13 1677) (iamlr14 1678) (iamlr15 1679)
(iamlr16 1680) (iamlr17 1681) (iamlr18 1682) (iamlr19 1683)
(iamlr20 1684) (iamlr21 1685) (iamlr22 1686) (iamlr23 1687)
(iamlr24 1688) (iamlr25 1689) (iamlr26 1690) (iamlr27 1691)
(iamlr28 1692) (iamlr29 1693) (iamlr30 1694) (iamlr31 1695)
(iamlr32 1696) (iamlr33 1697) (iamlr34 1698) (iamlr35 1699)
(iamlr36 1700) (iamlr37 1701) (iamlr38 1702) (iamlr39 1703)
(iamlr40 1704) (iamlr41 1705) (iamlr42 1706) (iamlr43 1707)
(iamlr44 1708) (iamlr45 1709) (iamlr46 1710) (iamlr47 1711)
(iamlr48 1712) (iamlr49 1713) (iamlr50 1714) (iamlr51 1715)
(iamlr52 1716) (iamlr53 1717) (iamlr54 1718) (iamlr55 1719)
(iamlr56 1720) (iamlr57 1721) (iamlr58 1722) (iamlr59 1723)
(iamlr60 1724) (iamlr61 1725) (iamlr62 1726) (iamlr63 1727)
(iampr0 1728) (iampr1 1729) (iampr2 1730) (iampr3 1731)
(iampr4 1732) (iampr5 1733) (iampr6 1734) (iampr7 1735)
(iampr8 1736) (iampr9 1737) (iampr10 1738) (iampr11 1739)
(iampr12 1740) (iampr13 1741) (iampr14 1742) (iampr15 1743)
(iampr16 1744) (iampr17 1745) (iampr18 1746) (iampr19 1747)
(iampr20 1748) (iampr21 1749) (iampr22 1750) (iampr23 1751)
(iampr24 1752) (iampr25 1753) (iampr26 1754) (iampr27 1755)
(iampr28 1756) (iampr29 1757) (iampr30 1758) (iampr31 1759)
(iampr32 1760) (iampr33 1761) (iampr34 1762) (iampr35 1763)
(iampr36 1764) (iampr37 1765) (iampr38 1766) (iampr39 1767)
(iampr40 1768) (iampr41 1769) (iampr42 1770) (iampr43 1771)
(iampr44 1772) (iampr45 1773) (iampr46 1774) (iampr47 1775)
(iampr48 1776) (iampr49 1777) (iampr50 1778) (iampr51 1779)
(iampr52 1780) (iampr53 1781) (iampr54 1782) (iampr55 1783)
(iampr56 1784) (iampr57 1785) (iampr58 1786) (iampr59 1787)
(iampr60 1788) (iampr61 1789) (iampr62 1790) (iampr63 1791)
(damlr0 1792) (damlr1 1793) (damlr2 1794) (damlr3 1795)
(damlr4 1796) (damlr5 1797) (damlr6 1798) (damlr7 1799)
(damlr8 1800) (damlr9 1801) (damlr10 1802) (damlr11 1803)
(damlr12 1804) (damlr13 1805) (damlr14 1806) (damlr15 1807)
(damlr16 1808) (damlr17 1809) (damlr18 1810) (damlr19 1811)
(damlr20 1812) (damlr21 1813) (damlr22 1814) (damlr23 1815)
(damlr24 1816) (damlr25 1817) (damlr26 1818) (damlr27 1819)
(damlr28 1820) (damlr29 1821) (damlr30 1822) (damlr31 1823)
(damlr32 1824) (damlr33 1825) (damlr34 1826) (damlr35 1827)
(damlr36 1828) (damlr37 1829) (damlr38 1830) (damlr39 1831)
(damlr40 1832) (damlr41 1833) (damlr42 1834) (damlr43 1835)
(damlr44 1836) (damlr45 1837) (damlr46 1838) (damlr47 1839)
(damlr48 1840) (damlr49 1841) (damlr50 1842) (damlr51 1843)
(damlr52 1844) (damlr53 1845) (damlr54 1846) (damlr55 1847)
(damlr56 1848) (damlr57 1849) (damlr58 1850) (damlr59 1851)
(damlr60 1852) (damlr61 1853) (damlr62 1854) (damlr63 1855)
(dampr0 1856) (dampr1 1857) (dampr2 1858) (dampr3 1859)
(dampr4 1860) (dampr5 1861) (dampr6 1862) (dampr7 1863)
(dampr8 1864) (dampr9 1865) (dampr10 1866) (dampr11 1867)
(dampr12 1868) (dampr13 1869) (dampr14 1870) (dampr15 1871)
(dampr16 1872) (dampr17 1873) (dampr18 1874) (dampr19 1875)
(dampr20 1876) (dampr21 1877) (dampr22 1878) (dampr23 1879)
(dampr24 1880) (dampr25 1881) (dampr26 1882) (dampr27 1883)
(dampr28 1884) (dampr29 1885) (dampr30 1886) (dampr31 1887)
(dampr32 1888) (dampr33 1889) (dampr34 1890) (dampr35 1891)
(dampr36 1892) (dampr37 1893) (dampr38 1894) (dampr39 1895)
(dampr40 1896) (dampr41 1897) (dampr42 1898) (dampr43 1899)
(dampr44 1900) (dampr45 1901) (dampr46 1902) (dampr47 1903)
(dampr48 1904) (dampr49 1905) (dampr50 1906) (dampr51 1907)
(dampr52 1908) (dampr53 1909) (dampr54 1910) (dampr55 1911)
(dampr56 1912) (dampr57 1913) (dampr58 1914) (dampr59 1915)
(dampr60 1916) (dampr61 1917) (dampr62 1918) (dampr63 1919)
(amcr 1920) (stbar 1921) (mmcr 1922)
(iamvr1 1925) (damvr1 1927)
(cxnr 1936) (ttbr 1937) (tplr 1938) (tppr 1939)
(tpxr 1940)
(timerh 1952) (timerl 1953) (timerd 1954)
(dcr 2048) (brr 2049) (nmar 2050) (btbr 2051)
(ibar0 2052) (ibar1 2053) (ibar2 2054) (ibar3 2055)
(dbar0 2056) (dbar1 2057) (dbar2 2058) (dbar3 2059)
(dbdr00 2060) (dbdr01 2061) (dbdr02 2062) (dbdr03 2063)
(dbdr10 2064) (dbdr11 2065) (dbdr12 2066) (dbdr13 2067)
(dbdr20 2068) (dbdr21 2069) (dbdr22 2070) (dbdr23 2071)
(dbdr30 2072) (dbdr31 2073) (dbdr32 2074) (dbdr33 2075)
(dbmr00 2076) (dbmr01 2077) (dbmr02 2078) (dbmr03 2079)
(dbmr10 2080) (dbmr11 2081) (dbmr12 2082) (dbmr13 2083)
(dbmr20 2084) (dbmr21 2085) (dbmr22 2086) (dbmr23 2087)
(dbmr30 2088) (dbmr31 2089) (dbmr32 2090) (dbmr33 2091)
(cpcfr 2304) (cpcr 2305) (cpsr 2306) (cptr 2307)
(cphsr0 2308) (cphsr1 2309) (cpesr0 2320) (cpesr1 2321)
(cpemr0 2322) (cpemr1 2323)
(iperr0 2324) (iperr1 2325) (ipjsr 2326) (ipjrr 2327)
(ipcsr0 2336) (ipcsr1 2337) (ipcwer0 2338) (ipcwer1 2339)
(ipcwr 2340)
(mbhsr 2352) (mbssr 2353) (mbrsr 2354) (mbsdr 2355)
(mbrdr 2356) (mbsmr 2357) (mbstr0 2359) (mbstr1 2360)
(slpr 2368) (sldr 2369) (slhsr 2370) (sltr 2371)
(slwr 2372)
(ihsr8 3848) (ihsr9 3849) (ihsr10 3850)
)
)
(define-hardware
(name h-spr)
(comment "special purpose registers")
(attrs PROFILE)
(type register UWI (4096))
(indices extern-keyword spr-names)
(get (index) (c-call UWI "@cpu@_h_spr_get_handler" index))
(set (index newval) (c-call VOID "@cpu@_h_spr_set_handler" index newval))
)
(define-pmacro (spr-pcsr) (reg h-spr 1))
(define-pmacro (spr-bpcsr) (reg h-spr 2))
(define-pmacro (spr-lr) (reg h-spr 272))
(define-pmacro (spr-lcr) (reg h-spr 273))
(define-pmacro (spr-iacc0h) (reg h-spr 280))
(define-pmacro (spr-iacc0l) (reg h-spr 281))
(define-pmacro (spr-sr0) (reg h-spr 768))
(define-pmacro (spr-sr1) (reg h-spr 769))
(define-pmacro (spr-sr2) (reg h-spr 770))
(define-pmacro (spr-sr3) (reg h-spr 771))
; Accumulator guard. Actually a subset of the SPR registers, but those SPRs
; are read-only in most insns. This hardware element is used by those insns
; which have direct access (mwtaccg, mrdaccg).
(define-keyword
(name accg-names)
(print-name h-accg)
(prefix "")
(values
(accg0 0)(accg1 1)(accg2 2)(accg3 3)
(accg4 4)(accg5 5)(accg6 6)(accg7 7)
(accg8 8)(accg9 9)(accg10 10)(accg11 11)
(accg12 12)(accg13 13)(accg14 14)(accg15 15)
(accg16 16)(accg17 17)(accg18 18)(accg19 19)
(accg20 20)(accg21 21)(accg22 22)(accg23 23)
(accg24 24)(accg25 25)(accg26 26)(accg27 27)
(accg28 28)(accg29 29)(accg30 30)(accg31 31)
(accg32 32)(accg33 33)(accg34 34)(accg35 35)
(accg36 36)(accg37 37)(accg38 38)(accg39 39)
(accg40 40)(accg41 41)(accg42 42)(accg43 43)
(accg44 44)(accg45 45)(accg46 46)(accg47 47)
(accg48 48)(accg49 49)(accg50 50)(accg51 51)
(accg52 52)(accg53 53)(accg54 54)(accg55 55)
(accg56 56)(accg57 57)(accg58 58)(accg59 59)
(accg60 60)(accg61 61)(accg62 62)(accg63 63)
)
)
(define-hardware
(name h-accg)
(comment "accumulator guard")
(attrs PROFILE VIRTUAL)
(type register UWI (64))
(indices extern-keyword accg-names)
(get (index)
(and (reg h-spr (add index 1472)) #xff))
(set (index newval)
(set (raw-reg UWI h-spr (add index 1472)) (and newval #xff)))
)
; 40 bit accumulator. Composed of ACCG and ACC registers concatenated, but
; referenced more often as the composed 40 bits.
(define-keyword
(name acc-names)
(print-name h-acc40)
(prefix "")
(values
(acc0 0)(acc1 1)(acc2 2)(acc3 3)(acc4 4)(acc5 5)(acc6 6)(acc7 7)
(acc8 8)(acc9 9)(acc10 10)(acc11 11)(acc12 12)(acc13 13)(acc14 14)(acc15 15)
(acc16 16)(acc17 17)(acc18 18)(acc19 19)(acc20 20)(acc21 21)(acc22 22)(acc23 23)
(acc24 24)(acc25 25)(acc26 26)(acc27 27)(acc28 28)(acc29 29)(acc30 30)(acc31 31)
(acc32 32)(acc33 33)(acc34 34)(acc35 35)(acc36 36)(acc37 37)(acc38 38)(acc39 39)
(acc40 40)(acc41 41)(acc42 42)(acc43 43)(acc44 44)(acc45 45)(acc46 46)(acc47 47)
(acc48 48)(acc49 49)(acc50 50)(acc51 51)(acc52 52)(acc53 53)(acc54 54)(acc55 55)
(acc56 56)(acc57 57)(acc58 58)(acc59 59)(acc60 60)(acc61 61)(acc62 62)(acc63 63)
)
)
(define-hardware
(name h-acc40S)
(comment "40 bit signed accumulator")
(attrs PROFILE VIRTUAL)
(type register DI (64))
(indices extern-keyword acc-names)
; The accumlator is made up of two 32 bit registers, accgi/acci.
; We want to extract this as a combined 40 signed bits
(get (index)
(or DI
(sll DI (ext DI (trunc QI (reg h-spr (add index 1472))))
32)
(zext DI (reg h-spr (add index 1408)))))
; Bits 40-63 are not written. raw-reg is used to bypass read-only restrictions
; on ACC and ACCG registers
(set (index newval)
(sequence ()
(c-call VOID "frv_check_spr_write_access" (add index 1408))
(set (raw-reg UWI h-spr
(add index 1472)) (and (srl newval 32) #xff))
(set (raw-reg UWI h-spr
(add index 1408)) (trunc USI newval))))
)
(define-hardware
(name h-acc40U)
(comment "40 bit unsigned accumulator")
(attrs PROFILE VIRTUAL)
(type register DI (64))
(indices extern-keyword acc-names)
; The accumlator is made up of two 32 bit registers, accgi/acci.
; We want to extract this as a combined 40 unsigned bits
(get (index)
(or DI
(sll DI (zext DI (reg h-spr (add index 1472))) 32)
(zext DI (reg h-spr (add index 1408)))))
; Bits 40-63 are not written. raw-reg is used to bypass read-only restrictions
; on ACC and ACCG registers
(set (index newval)
(sequence ()
(c-call VOID "frv_check_spr_write_access" (add index 1408))
(set (raw-reg UWI h-spr
(add index 1472)) (and (srl newval 32) #xff))
(set (raw-reg UWI h-spr
(add index 1408)) (trunc USI newval))))
)
; 64-bit signed accumulator. Composed of iacc0h and iacc0l registers
; concatenated, but referenced more often as the composed 64 bits.
(define-keyword
; This is totally hokey -- I have to have an index!
(name iacc0-names)
(print-name h-iacc0)
(prefix "")
(values (iacc0 0))
)
(define-hardware
(name h-iacc0)
(comment "64 bit signed accumulator")
(attrs PROFILE VIRTUAL (MACH fr400,fr450))
(type register DI (1))
(indices extern-keyword iacc0-names)
; The single 64-bit integer accumulator is made up of two 32 bit
; registers, iacc0h and iacc0l. We want to extract this as a
; combined 64 signed bits.
(get (idx) (or DI (sll DI (ext DI (spr-iacc0h)) 32) (zext DI (spr-iacc0l))))
(set (idx newval)
(sequence ()
(set (spr-iacc0h) (trunc SI (srl newval 32)))
(set (spr-iacc0l) (trunc SI newval))))
)
; Integer condition code registers (CCR)
;
; The individual sub registers bits of the CCR are referenced more often than
; the entire register so set them directly. We can assemble the
; entire register when necessary.
;
(define-keyword
(name iccr-names)
(print-name h-iccr)
(prefix "")
(values (icc0 0) (icc1 1) (icc2 2) (icc3 3))
)
(define-hardware
(name h-iccr)
(comment "Integer condition code registers")
(attrs PROFILE)
(type register UQI (4))
(indices extern-keyword iccr-names)
)
; Floating point condition code registers (CCR)
;
; The individual sub registers bits of the CCR are referenced more often than
; the entire register so set them directly. We can assemble the
; entire register when necessary.
;
(define-keyword
(name fccr-names)
(print-name h-fccr)
(prefix "")
(values (fcc0 0) (fcc1 1) (fcc2 2) (fcc3 3))
)
(define-hardware
(name h-fccr)
(comment "Floating point condition code registers")
(attrs PROFILE)
(type register UQI (4))
(indices extern-keyword fccr-names)
)
; C condition code registers (CCCR)
;
(define-keyword
(name cccr-names)
(print-name h-cccr)
(prefix "")
(values (cc0 0) (cc1 1) (cc2 2) (cc3 3) (cc4 4) (cc5 5) (cc6 6) (cc7 7))
)
(define-hardware
(name h-cccr)
(comment "Condition code registers")
(attrs PROFILE)
(type register UQI (8))
(indices extern-keyword cccr-names)
)
; Dummy hardware used to define packing bit on insns
;
(define-hardware
(name h-pack)
(comment "Packing bit dummy hardware")
(type immediate (UINT 1))
(values keyword "" (("" 1) (".p" 0) (".P" 0)))
)
; Dummy hardware used to define hint field for branches always taken
;
(define-hardware
(name h-hint-taken)
(comment "Branch taken hint dummy hardware")
(type immediate (UINT 1))
; The order of these is important. We want '2' to get written by default,
; but we also want the docoder/disassembler to allow the values '0', '1' and
; '3'.
(values keyword "" (("" 2) ("" 0) ("" 1) ("" 3)))
)
; Dummy hardware used to define hint field for branches never taken
;
(define-hardware
(name h-hint-not-taken)
(comment "Branch not taken hint dummy hardware")
(type immediate (UINT 1))
; The order of these is important. We want '0' to get written by default,
; but we also want the docoder/disassembler to allow the values '1', '2' and
; '3'.
(values keyword "" (("" 0) ("" 1) ("" 2) ("" 3)))
)
; Instruction Operands.
; These entries provide a layer between the assembler and the raw hardware
; description, and are used to refer to hardware elements in the semantic
; code. Usually there's a bit of over-specification, but in more complicated
; instruction sets there isn't.
; FRV specific operand attributes:
(define-attr
(for operand)
(type boolean)
(name HASH-PREFIX)
(comment "immediates have an optional '#' prefix")
)
; ??? Convention says this should be o-sr, but then the insn definitions
; should refer to o-sr which is clumsy. The "o-" could be implicit, but
; then it should be implicit for all the symbols here, but then there would
; be confusion between (f-)simm8 and (h-)simm8.
; So for now the rule is exactly as it appears here.
; dnmop: define-normal-mode-operand: temporary, pending potential removal
; of modes from h/w.
(define-pmacro (dnmop xname xcomment xattrs xtype xindex xmode)
(define-operand
(name xname)
(comment xcomment)
(.splice attrs (.unsplice xattrs))
(type xtype)
(index xindex)
(mode xmode)
)
)
; dnpmop: define-normal-parsed-mode-operand: Normal mode operand with parse handler
(define-pmacro (dnpmop xname xcomment xattrs xtype xindex xmode xparse)
(define-operand
(name xname)
(comment xcomment)
(.splice attrs (.unsplice xattrs))
(type xtype)
(index xindex)
(mode xmode)
(handlers (parse xparse))
)
)
(dnop pack "packing bit" () h-pack f-pack)
(dnmop GRi "source register 1" () h-gr f-GRi SI)
(dnmop GRj "source register 2" () h-gr f-GRj SI)
(dnmop GRk "destination register" () h-gr f-GRk SI)
(dnmop GRkhi "destination register" () h-gr_hi f-GRk UHI)
(dnmop GRklo "destination register" () h-gr_lo f-GRk UHI)
(dnpmop GRdoublek "destination register" () h-gr_double f-GRk DI "even_register")
(dnmop ACC40Si "signed accumulator" () h-acc40S f-ACC40Si DI)
(dnmop ACC40Ui "unsigned accumulator" () h-acc40U f-ACC40Ui UDI)
(dnmop ACC40Sk "target accumulator" () h-acc40S f-ACC40Sk DI)
(dnmop ACC40Uk "target accumulator" () h-acc40U f-ACC40Uk UDI)
(dnmop ACCGi "source register" () h-accg f-ACCGi UWI)
(dnmop ACCGk "target register" () h-accg f-ACCGk UWI)
(dnmop CPRi "source register" ((MACH frv)) h-cpr f-CPRi SI)
(dnmop CPRj "source register" ((MACH frv)) h-cpr f-CPRj SI)
(dnmop CPRk "destination register" ((MACH frv)) h-cpr f-CPRk SI)
(dnpmop CPRdoublek "destination register" ((MACH frv)) h-cpr_double f-CPRk DI "even_register")
; floating point operands
(dnmop FRinti "source register 1" () h-fr_int f-FRi SI)
(dnmop FRintj "source register 2" () h-fr_int f-FRj SI)
(dnmop FRintk "target register" () h-fr_int f-FRk SI)
(dnmop FRi "source register 1" () h-fr f-FRi SF)
(dnmop FRj "source register 2" () h-fr f-FRj SF)
(dnmop FRk "destination register" () h-fr f-FRk SF)
(dnmop FRkhi "destination register" () h-fr_hi f-FRk UHI)
(dnmop FRklo "destination register" () h-fr_lo f-FRk UHI)
(dnpmop FRdoublei "source register 1" () h-fr_double f-FRi DF "even_register")
(dnpmop FRdoublej "source register 2" () h-fr_double f-FRj DF "even_register")
(dnpmop FRdoublek "target register" () h-fr_double f-FRk DF "even_register")
(dnop CRi "source register 1" () h-cccr f-CRi)
(dnop CRj "source register 2" () h-cccr f-CRj)
(dnop CRj_int "destination register" () h-cccr f-CRj_int)
(dnop CRj_float "destination register" () h-cccr f-CRj_float)
(dnop CRk "destination register" () h-cccr f-CRk)
(dnop CCi "condition register" () h-cccr f-CCi)
(dnop ICCi_1 "condition register" () h-iccr f-ICCi_1)
(dnop ICCi_2 "condition register" () h-iccr f-ICCi_2)
(dnop ICCi_3 "condition register" () h-iccr f-ICCi_3)
(dnop FCCi_1 "condition register" () h-fccr f-FCCi_1)
(dnop FCCi_2 "condition register" () h-fccr f-FCCi_2)
(dnop FCCi_3 "condition register" () h-fccr f-FCCi_3)
(dnop FCCk "condition register" () h-fccr f-FCCk)
(dnop eir "exception insn reg" () h-uint f-eir)
(dnop s10 "10 bit signed immediate" (HASH-PREFIX) h-sint f-s10)
(dnop u16 "16 bit unsigned immediate" (HASH-PREFIX) h-uint f-u16)
(dnop s16 "16 bit signed immediate" (HASH-PREFIX) h-sint f-s16)
(dnop s6 "6 bit signed immediate" (HASH-PREFIX) h-sint f-s6)
(dnop s6_1 "6 bit signed immediate" (HASH-PREFIX) h-sint f-s6_1)
(dnop u6 "6 bit unsigned immediate" (HASH-PREFIX) h-uint f-u6)
(dnop s5 "5 bit signed immediate" (HASH-PREFIX) h-sint f-s5)
(dnop cond "conditional arithmetic" (HASH-PREFIX) h-uint f-cond)
(dnop ccond "lr branch condition" (HASH-PREFIX) h-uint f-ccond)
(dnop hint "2 bit branch predictor" (HASH-PREFIX) h-uint f-hint)
(dnop hint_taken "2 bit branch predictor" () h-hint-taken f-hint)
(dnop hint_not_taken "2 bit branch predictor" () h-hint-not-taken f-hint)
(dnop LI "link indicator" () h-uint f-LI)
(dnop lock "cache lock indicator" (HASH-PREFIX) h-uint f-lock)
(dnop debug "debug mode indicator" (HASH-PREFIX) h-uint f-debug)
(dnop ae "all entries indicator" (HASH-PREFIX) h-uint f-ae)
(dnop label16 "18 bit pc relative address" () h-iaddr f-label16)
(dnop LRAE "Load Real Address E flag" () h-uint f-LRAE)
(dnop LRAD "Load Real Address D flag" () h-uint f-LRAD)
(dnop LRAS "Load Real Address S flag" () h-uint f-LRAS)
(dnop TLBPRopx "TLB Probe operation number" () h-uint f-TLBPRopx)
(dnop TLBPRL "TLB Probe L flag" () h-uint f-TLBPRL)
(define-operand
(name A0)
(comment "A==0 operand of mclracc")
(attrs)
(type h-uint)
(index f-A)
(mode USI)
(handlers (parse "A0"))
)
(define-operand
(name A1)
(comment "A==1 operand of mclracc")
(attrs)
(type h-uint)
(index f-A)
(mode USI)
(handlers (parse "A1"))
)
(define-operand
(name FRintieven)
(comment "(even) source register 1")
(attrs)
(type h-fr_int)
(index f-FRi)
(mode SI)
(handlers (parse "even_register"))
)
(define-operand
(name FRintjeven)
(comment "(even) source register 2")
(attrs)
(type h-fr_int)
(index f-FRj)
(mode SI)
(handlers (parse "even_register"))
)
(define-operand
(name FRintkeven)
(comment "(even) target register")
(attrs)
(type h-fr_int)
(index f-FRk)
(mode SI)
(handlers (parse "even_register"))
)
(define-operand
(name d12)
(comment "12 bit signed immediate")
(attrs)
(type h-sint)
(index f-d12)
(handlers (parse "d12"))
)
(define-operand
(name s12)
(comment "12 bit signed immediate")
(attrs HASH-PREFIX)
(type h-sint)
(index f-d12)
(handlers (parse "s12"))
)
(define-operand
(name u12)
(comment "12 bit signed immediate")
(attrs HASH-PREFIX)
(type h-sint)
(index f-u12)
(handlers (parse "u12"))
)
(define-operand
(name spr)
(comment "special purpose register")
(attrs)
(type h-spr)
(index f-spr)
(handlers (parse "spr") (print "spr"))
)
(define-operand
(name ulo16)
(comment "16 bit unsigned immediate, for #lo()")
(attrs)
(type h-uint)
(index f-u16)
(handlers (parse "ulo16") (print "lo"))
)
(define-operand
(name slo16)
(comment "16 bit unsigned immediate, for #lo()")
(attrs)
(type h-sint)
(index f-s16)
(handlers (parse "uslo16") (print "lo"))
)
(define-operand
(name uhi16)
(comment "16 bit unsigned immediate, for #hi()")
(attrs)
(type h-uint)
(index f-u16)
(handlers (parse "uhi16") (print "hi"))
)
(define-operand
(name label24)
(comment "26 bit pc relative address")
(attrs)
(type h-iaddr)
(index f-label24)
(mode SI)
(handlers (parse "call_label"))
)
; operands representing hardware
;
(dnop psr_esr "PSR.ESR bit" (SEM-ONLY) h-psr_esr f-nil)
(dnop psr_s "PSR.S bit" (SEM-ONLY) h-psr_s f-nil)
(dnop psr_ps "PSR.PS bit" (SEM-ONLY) h-psr_ps f-nil)
(dnop psr_et "PSR.ET bit" (SEM-ONLY) h-psr_et f-nil)
(dnop bpsr_bs "BPSR.BS bit" (SEM-ONLY) h-bpsr_bs f-nil)
(dnop bpsr_bet "BPSR.BET bit" (SEM-ONLY) h-bpsr_bet f-nil)
(dnop tbr_tba "TBR.TBA" (SEM-ONLY) h-tbr_tba f-nil)
(dnop tbr_tt "TBR.TT" (SEM-ONLY) h-tbr_tt f-nil)
; Null operands
;
(define-pmacro (ICCi_1-null) (f-ICCi_1-null 0))
(define-pmacro (ICCi_2-null) (f-ICCi_2-null 0))
(define-pmacro (ICCi_3-null) (f-ICCi_3-null 0))
(define-pmacro (FCCi_1-null) (f-FCCi_1-null 0))
(define-pmacro (FCCi_2-null) (f-FCCi_2-null 0))
(define-pmacro (FCCi_3-null) (f-FCCi_3-null 0))
(define-pmacro (rs-null) (f-rs-null 0))
(define-pmacro (GRi-null) (f-GRi-null 0))
(define-pmacro (GRj-null) (f-GRj-null 0))
(define-pmacro (GRk-null) (f-GRk-null 0))
(define-pmacro (FRi-null) (f-FRi-null 0))
(define-pmacro (FRj-null) (f-FRj-null 0))
(define-pmacro (ACCj-null) (f-ACCj-null 0))
(define-pmacro (rd-null) (f-rd-null 0))
(define-pmacro (cond-null) (f-cond-null 0))
(define-pmacro (ccond-null) (f-ccond-null 0))
(define-pmacro (s12-null) (f-s12-null 0))
(define-pmacro (label16-null) (f-label16-null 0))
(define-pmacro (misc-null-1) (f-misc-null-1 0))
(define-pmacro (misc-null-2) (f-misc-null-2 0))
(define-pmacro (misc-null-3) (f-misc-null-3 0))
(define-pmacro (misc-null-4) (f-misc-null-4 0))
(define-pmacro (misc-null-5) (f-misc-null-5 0))
(define-pmacro (misc-null-6) (f-misc-null-6 0))
(define-pmacro (misc-null-7) (f-misc-null-7 0))
(define-pmacro (misc-null-8) (f-misc-null-8 0))
(define-pmacro (misc-null-9) (f-misc-null-9 0))
(define-pmacro (misc-null-10) (f-misc-null-10 0))
(define-pmacro (misc-null-11) (f-misc-null-11 0))
(define-pmacro (LRA-null) (f-LRA-null 0))
(define-pmacro (TLBPR-null) (f-TLBPR-null 0))
(define-pmacro (LI-on) (f-LI-on 1))
(define-pmacro (LI-off) (f-LI-off 0))
; Instruction definitions.
;
; Notes:
; - dni is short for "define-normal-instruction"
; - Macros are used to represent each insn format. These should be used as much
; as possible unless an insn has exceptional behaviour
;
; Commonly used Macros
;
; Specific registers
;
; Integer condition code manipulation
;
(define-pmacro (set-z-and-n icc x)
(if (eq x 0)
(set icc (or (and icc #x7) #x4))
(if (lt x 0)
(set icc (or (and icc #xb) #x8))
(set icc (and icc #x3))))
)
(define-pmacro (set-n icc val)
(if (eq val 0)
(set icc (and icc #x7))
(set icc (or icc #x8)))
)
(define-pmacro (set-z icc val)
(if (eq val 0)
(set icc (and icc #xb))
(set icc (or icc #x4)))
)
(define-pmacro (set-v icc val)
(if (eq val 0)
(set icc (and icc #xd))
(set icc (or icc #x2)))
)
(define-pmacro (set-c icc val)
(if (eq val 0)
(set icc (and icc #xe))
(set icc (or icc #x1)))
)
(define-pmacro (nbit icc)
(trunc BI (srl (and icc #x8) 3))
)
(define-pmacro (zbit icc)
(trunc BI (srl (and icc #x4) 2))
)
(define-pmacro (vbit icc)
(trunc BI (srl (and icc #x2) 1))
)
(define-pmacro (cbit icc)
(trunc BI (and icc #x1))
)
(define-pmacro (ebit icc)
(trunc BI (srl (and icc #x8) 3))
)
(define-pmacro (lbit icc)
(trunc BI (srl (and icc #x4) 2))
)
(define-pmacro (gbit icc)
(trunc BI (srl (and icc #x2) 1))
)
(define-pmacro (ubit icc)
(trunc BI (and icc #x1))
)
; FRV insns
;
;
; Format: INT, Logic, Shift r-r
;
(define-pmacro (int-logic-r-r name operation op ope comment)
(dni name
(comment)
((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1)
(FR400-MAJOR I-1) (FR450-MAJOR I-1))
(.str name "$pack $GRi,$GRj,$GRk")
(+ pack GRk op GRi (ICCi_1-null) ope GRj)
(set GRk (operation GRi GRj))
((fr400 (unit u-integer)) (fr450 (unit u-integer))
(fr500 (unit u-integer)) (fr550 (unit u-integer)))
)
)
(int-logic-r-r add add OP_00 OPE2_00 "add reg/reg")
(int-logic-r-r sub sub OP_00 OPE2_04 "sub reg/reg")
(int-logic-r-r and and OP_01 OPE2_00 "and reg/reg")
(int-logic-r-r or or OP_01 OPE2_02 "or reg/reg")
(int-logic-r-r xor xor OP_01 OPE2_04 "xor reg/reg")
(dni not
("not")
((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1)
(FR400-MAJOR I-1) (FR450-MAJOR I-1))
("not$pack $GRj,$GRk")
(+ pack GRk OP_01 (rs-null) (ICCi_1-null) OPE2_06 GRj)
(set GRk (inv GRj))
((fr400 (unit u-integer)) (fr450 (unit u-integer))
(fr500 (unit u-integer)) (fr550 (unit u-integer)))
)
(dni sdiv
"signed division"
((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2)
(FR400-MAJOR I-1) (FR450-MAJOR I-1))
"sdiv$pack $GRi,$GRj,$GRk"
(+ pack GRk OP_00 GRi (ICCi_1-null) OPE2_0E GRj)
(sequence ()
(c-call VOID "@cpu@_signed_integer_divide"
GRi GRj (index-of GRk) 0)
(clobber GRk))
((fr400 (unit u-idiv)) (fr450 (unit u-idiv))
(fr500 (unit u-idiv)) (fr550 (unit u-idiv)))
)
(dni nsdiv
"non excepting signed division"
((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2) NON-EXCEPTING
(MACH simple,tomcat,fr500,fr550,frv))
"nsdiv$pack $GRi,$GRj,$GRk"
(+ pack GRk OP_01 GRi (ICCi_1-null) OPE2_0E GRj)
(sequence ()
(c-call VOID "@cpu@_signed_integer_divide"
GRi GRj (index-of GRk) 1)
(clobber GRk))
((fr500 (unit u-idiv)) (fr550 (unit u-idiv)))
)
(dni udiv
"unsigned division reg/reg"
((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2)
(FR400-MAJOR I-1) (FR450-MAJOR I-1))
"udiv$pack $GRi,$GRj,$GRk"
(+ pack GRk OP_00 GRi (ICCi_1-null) OPE2_0F GRj)
(sequence ()
(c-call VOID "@cpu@_unsigned_integer_divide"
GRi GRj (index-of GRk) 0)
(clobber GRk))
((fr400 (unit u-idiv)) (fr450 (unit u-idiv))
(fr500 (unit u-idiv)) (fr550 (unit u-idiv)))
)
(dni nudiv
"non excepting unsigned division"
((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2) NON-EXCEPTING
(MACH simple,tomcat,fr500,fr550,frv))
"nudiv$pack $GRi,$GRj,$GRk"
(+ pack GRk OP_01 GRi (ICCi_1-null) OPE2_0F GRj)
(sequence ()
(c-call VOID "@cpu@_unsigned_integer_divide"
GRi GRj (index-of GRk) 1)
(clobber GRk))
((fr500 (unit u-idiv)) (fr550 (unit u-idiv)))
)
; Multiplication
;
(define-pmacro (multiply-r-r name signop op ope comment)
(dni name
(comment)
((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2)
(FR400-MAJOR I-1) (FR450-MAJOR I-1))
(.str name "$pack $GRi,$GRj,$GRdoublek")
(+ pack GRdoublek op GRi (ICCi_1-null) ope GRj)
(set GRdoublek (mul DI (signop DI GRi) (signop DI GRj)))
((fr400 (unit u-imul)) (fr450 (unit u-imul))
(fr500 (unit u-imul)) (fr550 (unit u-imul)))
)
)
(multiply-r-r smul ext OP_00 OPE2_08 "signed multiply reg/reg")
(multiply-r-r umul zext OP_00 OPE2_0A "unsigned multiply reg/reg")
; Multiplication with integer accumulator IACC
;
(define-pmacro (iacc-set value)
(set (reg h-iacc0 0) value))
(define-pmacro (iacc-add value)
(set (reg h-iacc0 0)
(cond DI
((andif (andif (gt value 0) (gt (reg h-iacc0 0) 0))
(lt (sub DI #x7fffffffffffffff value) (reg h-iacc0 0)))
; Positive overflow
(const DI #x7fffffffffffffff))
((andif (andif (lt value 0) (lt (reg h-iacc0 0) 0))
(gt (sub DI #x8000000000000000 value) (reg h-iacc0 0)))
; Negative overflow
(const DI #x8000000000000000))
(else
(add DI (reg h-iacc0 0) value))))
)
(define-pmacro (iacc-sub value)
(set (reg h-iacc0 0)
(cond DI
((andif (andif (lt value 0) (gt (reg h-iacc0 0) 0))
(lt (add DI #x7fffffffffffffff value) (reg h-iacc0 0)))
; Positive overflow
(const DI #x7fffffffffffffff))
((andif (andif (gt value 0) (lt (reg h-iacc0 0) 0))
(gt (add DI #x8000000000000000 value) (reg h-iacc0 0)))
; Negative overflow
(const DI #x8000000000000000))
(else
(sub DI (reg h-iacc0 0) value))))
)
(define-pmacro (iacc-multiply-r-r name operation op ope comment)
(dni name
(comment)
((UNIT IACC) (MACH fr400,fr450)
(FR400-MAJOR I-1) (FR450-MAJOR I-1) AUDIO)
(.str name "$pack $GRi,$GRj")
(+ pack (rd-null) op GRi ope GRj)
((.sym iacc- operation) (mul DI (ext DI GRi) (ext DI GRj)))
((fr400 (unit u-integer)) (fr450 (unit u-integer)))
)
)
(iacc-multiply-r-r smu set OP_46 OPE1_05 "Signed multiply reg/reg/iacc")
(iacc-multiply-r-r smass add OP_46 OPE1_06 "Signed multiply/add reg/reg/iacc")
(iacc-multiply-r-r smsss sub OP_46 OPE1_07 "Signed multiply/sub reg/reg/iacc")
(define-pmacro (int-shift-r-r name op ope comment)
(dni name
(comment)
((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1)
(FR400-MAJOR I-1) (FR450-MAJOR I-1))
(.str name "$pack $GRi,$GRj,$GRk")
(+ pack GRk op GRi (ICCi_1-null) ope GRj)
(set GRk (name GRi (and GRj #x1f)))
((fr400 (unit u-integer)) (fr450 (unit u-integer))
(fr500 (unit u-integer)) (fr550 (unit u-integer)))
)
)
(int-shift-r-r sll OP_01 OPE2_08 "shift left logical reg/reg")
(int-shift-r-r srl OP_01 OPE2_0A "shift right logical reg/reg")
(int-shift-r-r sra OP_01 OPE2_0C "shift right arith reg/reg")
(dni slass
"shift left arith reg/reg with saturation"
((UNIT IALL) (MACH fr400,fr450)
(FR400-MAJOR I-1) (FR450-MAJOR I-1) AUDIO)
"slass$pack $GRi,$GRj,$GRk"
(+ pack GRk OP_46 GRi OPE1_02 GRj)
(set GRk (c-call SI "@cpu@_shift_left_arith_saturate" GRi GRj))
()
)
(dni scutss
"Integer accumulator cut with saturation"
((UNIT I0) (MACH fr400,fr450)
(FR400-MAJOR I-1) (FR450-MAJOR I-1) AUDIO)
"scutss$pack $GRj,$GRk"
(+ pack GRk OP_46 (rs-null) OPE1_04 GRj)
(set GRk (c-call SI "@cpu@_iacc_cut" (reg h-iacc0 0) GRj))
()
)
(define-pmacro (scan-semantics arg1 arg2 targ)
(sequence ((WI tmp1) (WI tmp2))
(set tmp1 arg1)
(set tmp2 (sra arg2 1))
(set targ (c-call WI "@cpu@_scan_result" (xor tmp1 tmp2))))
)
(dni scan
"scan"
((UNIT SCAN) (FR500-MAJOR I-1) (FR550-MAJOR I-1)
(FR400-MAJOR I-1) (FR450-MAJOR I-1))
"scan$pack $GRi,$GRj,$GRk"
(+ pack GRk OP_0B GRi (ICCi_1-null) OPE2_00 GRj)
(scan-semantics GRi GRj GRk)
((fr400 (unit u-integer)) (fr450 (unit u-integer))
(fr500 (unit u-integer)) (fr550 (unit u-integer)))
)
; Format: conditional INT, Logic, Shift r-r
;
(define-pmacro (conditional-int-logic name operation op ope comment)
(dni name
(comment)
((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1)
(FR400-MAJOR I-1) (FR450-MAJOR I-1) CONDITIONAL)
(.str name "$pack $GRi,$GRj,$GRk,$CCi,$cond")
(+ pack GRk op GRi CCi cond ope GRj)
(if (eq CCi (or cond 2))
(set GRk (operation GRi GRj)))
((fr400 (unit u-integer)) (fr450 (unit u-integer))
(fr500 (unit u-integer)) (fr550 (unit u-integer)))
)
)
(conditional-int-logic cadd add OP_58 OPE4_0 "conditional add")
(conditional-int-logic csub sub OP_58 OPE4_1 "conditional sub")
(conditional-int-logic cand and OP_5A OPE4_0 "conditional and")
(conditional-int-logic cor or OP_5A OPE4_1 "conditional or")
(conditional-int-logic cxor xor OP_5A OPE4_2 "conditional xor")
(dni cnot
"conditional not"
((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1)
(FR400-MAJOR I-1) (FR450-MAJOR I-1) CONDITIONAL)
"cnot$pack $GRj,$GRk,$CCi,$cond"
(+ pack GRk OP_5A (rs-null) CCi cond OPE4_3 GRj)
(if (eq CCi (or cond 2))
(set GRk (inv GRj)))
((fr400 (unit u-integer)) (fr450 (unit u-integer))
(fr500 (unit u-integer)) (fr550 (unit u-integer)))
)
(dni csmul
"conditional signed multiply"
((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2)
(FR400-MAJOR I-1) (FR450-MAJOR I-1) CONDITIONAL)
"csmul$pack $GRi,$GRj,$GRdoublek,$CCi,$cond"
(+ pack GRdoublek OP_58 GRi CCi cond OPE4_2 GRj)
(if (eq CCi (or cond 2))
(set GRdoublek (mul DI (ext DI GRi) (ext DI GRj))))
((fr400 (unit u-imul)) (fr450 (unit u-imul))
(fr500 (unit u-imul)) (fr550 (unit u-imul)))
)
(dni csdiv
"conditional signed division"
((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2)
(FR400-MAJOR I-1) (FR450-MAJOR I-1) CONDITIONAL)
"csdiv$pack $GRi,$GRj,$GRk,$CCi,$cond"
(+ pack GRk OP_58 GRi CCi cond OPE4_3 GRj)
(if (eq CCi (or cond 2))
(sequence ()
(c-call VOID "@cpu@_signed_integer_divide"
GRi GRj (index-of GRk) 0)
(clobber GRk)))
((fr400 (unit u-idiv)) (fr450 (unit u-idiv))
(fr500 (unit u-idiv)) (fr550 (unit u-idiv)))
)
(dni cudiv
"conditional unsigned division"
((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2)
(FR400-MAJOR I-1) (FR450-MAJOR I-1) CONDITIONAL)
"cudiv$pack $GRi,$GRj,$GRk,$CCi,$cond"
(+ pack GRk OP_59 GRi CCi cond OPE4_3 GRj)
(if (eq CCi (or cond 2))
(sequence ()
(c-call VOID "@cpu@_unsigned_integer_divide"
GRi GRj (index-of GRk) 0)
(clobber GRk)))
((fr400 (unit u-idiv)) (fr450 (unit u-idiv))
(fr500 (unit u-idiv)) (fr550 (unit u-idiv)))
)
(define-pmacro (conditional-shift name operation op ope comment)
(dni name
(comment)
((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1)
(FR400-MAJOR I-1) (FR450-MAJOR I-1) CONDITIONAL)
(.str name "$pack $GRi,$GRj,$GRk,$CCi,$cond")
(+ pack GRk op GRi CCi cond ope GRj)
(if (eq CCi (or cond 2))
(set GRk (operation GRi (and GRj #x1f))))
((fr400 (unit u-integer)) (fr450 (unit u-integer))
(fr500 (unit u-integer)) (fr550 (unit u-integer)))
)
)
(conditional-shift csll sll OP_5C OPE4_0 "conditional shift left logical")
(conditional-shift csrl srl OP_5C OPE4_1 "conditional shift right logical")
(conditional-shift csra sra OP_5C OPE4_2 "conditional shift right arith")
(dni cscan
"conditional scan"
((UNIT SCAN) (FR500-MAJOR I-1) (FR550-MAJOR I-1)
(FR400-MAJOR I-1) (FR450-MAJOR I-1) CONDITIONAL)
"cscan$pack $GRi,$GRj,$GRk,$CCi,$cond"
(+ pack GRk OP_65 GRi CCi cond OPE4_3 GRj)
(if (eq CCi (or cond 2))
(scan-semantics GRi GRj GRk))
((fr400 (unit u-integer)) (fr450 (unit u-integer))
(fr500 (unit u-integer)) (fr550 (unit u-integer)))
)
; Format: INT, Logic, Shift, cc r-r
;
(define-pmacro (int-arith-cc-semantics operation icc)
(sequence ((BI tmp) (QI cc) (SI result))
(set cc icc)
(set tmp ((.sym operation -oflag) GRi GRj (const 0)))
(set-v cc tmp)
(set tmp ((.sym operation -cflag) GRi GRj (const 0)))
(set-c cc tmp)
(set result (operation GRi GRj))
(set-z-and-n cc result)
(set GRk result)
(set icc cc))
)
(define-pmacro (int-arith-cc-r-r name operation op ope comment)
(dni name
(comment)
((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1)
(FR400-MAJOR I-1) (FR450-MAJOR I-1))
(.str name "$pack $GRi,$GRj,$GRk,$ICCi_1")
(+ pack GRk op GRi ICCi_1 ope GRj)
(int-arith-cc-semantics operation ICCi_1)
((fr400 (unit u-integer)) (fr450 (unit u-integer))
(fr500 (unit u-integer)) (fr550 (unit u-integer)))
)
)
(int-arith-cc-r-r addcc add OP_00 OPE2_01 "add reg/reg, set icc")
(int-arith-cc-r-r subcc sub OP_00 OPE2_05 "sub reg/reg, set icc")
(define-pmacro (int-logic-cc-semantics op icc)
(sequence ((SI tmp))
(set tmp (op GRi GRj))
(set GRk tmp)
(set-z-and-n icc tmp))
)
(define-pmacro (int-logic-cc-r-r name op ope comment)
(dni (.sym name cc)
(comment)
((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1)
(FR400-MAJOR I-1) (FR450-MAJOR I-1))
(.str (.sym name cc) "$pack $GRi,$GRj,$GRk,$ICCi_1")
(+ pack GRk op GRi ICCi_1 ope GRj)
(int-logic-cc-semantics name ICCi_1)
((fr400 (unit u-integer)) (fr450 (unit u-integer))
(fr500 (unit u-integer)) (fr550 (unit u-integer)))
)
)
(int-logic-cc-r-r and OP_01 OPE2_01 "and reg/reg, set icc")
(int-logic-cc-r-r or OP_01 OPE2_03 "or reg/reg, set icc")
(int-logic-cc-r-r xor OP_01 OPE2_05 "xor reg/reg, set icc")
(define-pmacro (int-shift-cc-semantics op l-r icc)
(sequence ((WI shift) (SI tmp) (QI cc))
(set shift (and GRj #x1f))
(set cc (c-call QI (.str "@cpu@_set_icc_for_shift_" l-r)
GRi shift icc))
(set tmp (op GRi shift))
(set GRk tmp)
(set-z-and-n cc tmp)
(set icc cc))
)
(define-pmacro (int-shift-cc-r-r name l-r op ope comment)
(dni (.sym name cc)
(comment)
((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1)
(FR400-MAJOR I-1) (FR450-MAJOR I-1))
(.str (.sym name cc) "$pack $GRi,$GRj,$GRk,$ICCi_1")
(+ pack GRk op GRi ICCi_1 ope GRj)
(int-shift-cc-semantics name l-r ICCi_1)
((fr400 (unit u-integer)) (fr450 (unit u-integer))
(fr500 (unit u-integer)) (fr550 (unit u-integer)))
)
)
(int-shift-cc-r-r sll left OP_01 OPE2_09 "shift left logical reg/reg,set icc")
(int-shift-cc-r-r srl right OP_01 OPE2_0B "shift right logical reg/reg,set icc")
(int-shift-cc-r-r sra right OP_01 OPE2_0D "shift right arith reg/reg,set icc")
(define-pmacro (multiply-cc-semantics signop arg1 arg2 targ icc)
(sequence ((DI tmp) (QI cc))
(set cc icc)
(set tmp (mul DI (signop DI arg1) (signop DI arg2)))
(set-n cc (srl DI tmp 63))
(set-z cc (eq tmp 0))
(set targ tmp)
(set icc cc))
)
(define-pmacro (multiply-cc-r-r name signop op ope comment)
(dni name
(comment)
((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2)
(FR400-MAJOR I-1) (FR450-MAJOR I-1))
(.str name "$pack $GRi,$GRj,$GRdoublek,$ICCi_1")
(+ pack GRdoublek op GRi ICCi_1 ope GRj)
(multiply-cc-semantics signop GRi GRj GRdoublek ICCi_1)
((fr400 (unit u-imul)) (fr450 (unit u-imul))
(fr500 (unit u-imul)) (fr550 (unit u-imul)))
)
)
(multiply-cc-r-r smulcc ext OP_00 OPE2_09 "signed multiply reg/reg")
(multiply-cc-r-r umulcc zext OP_00 OPE2_0B "unsigned multiply reg/reg")
; Format: conditional INT, Logic, Shift, cc r-r
;
(define-pmacro (conditional-int-arith-cc name operation op ope comment)
(dni name
(comment)
((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1)
(FR400-MAJOR I-1) (FR450-MAJOR I-1) CONDITIONAL)
(.str name "$pack $GRi,$GRj,$GRk,$CCi,$cond")
(+ pack GRk op GRi CCi cond ope GRj)
(if (eq CCi (or cond 2))
(int-arith-cc-semantics operation
(reg h-iccr (and (index-of CCi) 3))))
((fr400 (unit u-integer)) (fr450 (unit u-integer))
(fr500 (unit u-integer)) (fr550 (unit u-integer)))
)
)
(conditional-int-arith-cc caddcc add OP_59 OPE4_0 "add, set icc")
(conditional-int-arith-cc csubcc sub OP_59 OPE4_1 "sub, set icc")
(dni csmulcc
"conditional signed multiply and set condition code"
((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2)
(FR400-MAJOR I-1) (FR450-MAJOR I-1) CONDITIONAL)
"csmulcc$pack $GRi,$GRj,$GRdoublek,$CCi,$cond"
(+ pack GRdoublek OP_59 GRi CCi cond OPE4_2 GRj)
(if (eq CCi (or cond 2))
(multiply-cc-semantics ext GRi GRj GRdoublek
(reg h-iccr (and (index-of CCi) 3))))
((fr400 (unit u-imul)) (fr450 (unit u-imul))
(fr500 (unit u-imul)) (fr550 (unit u-imul)))
)
(define-pmacro (conditional-int-logic-cc name operation op ope comment)
(dni name
(comment)
((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1)
(FR400-MAJOR I-1) (FR450-MAJOR I-1) CONDITIONAL)
(.str name "$pack $GRi,$GRj,$GRk,$CCi,$cond")
(+ pack GRk op GRi CCi cond ope GRj)
(if (eq CCi (or cond 2))
(int-logic-cc-semantics operation
(reg h-iccr (and (index-of CCi) 3))))
((fr400 (unit u-integer)) (fr450 (unit u-integer))
(fr500 (unit u-integer)) (fr550 (unit u-integer)))
)
)
(conditional-int-logic-cc candcc and OP_5B OPE4_0 "conditional and, set icc")
(conditional-int-logic-cc corcc or OP_5B OPE4_1 "conditional or , set icc")
(conditional-int-logic-cc cxorcc xor OP_5B OPE4_2 "conditional xor, set icc")
(define-pmacro (conditional-int-shift-cc name l-r op ope comment)
(dni (.sym c name cc)
(comment)
((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1)
(FR400-MAJOR I-1) (FR450-MAJOR I-1) CONDITIONAL)
(.str (.sym c name cc) "$pack $GRi,$GRj,$GRk,$CCi,$cond")
(+ pack GRk op GRi CCi cond ope GRj)
(if (eq CCi (or cond 2))
(int-shift-cc-semantics name l-r
(reg h-iccr (and (index-of CCi) 3))))
((fr400 (unit u-integer)) (fr450 (unit u-integer))
(fr500 (unit u-integer)) (fr550 (unit u-integer)))
)
)
(conditional-int-shift-cc sll left OP_5D OPE4_0 "shift left logical, set icc")
(conditional-int-shift-cc srl right OP_5D OPE4_1 "shift right logical, set icc")
(conditional-int-shift-cc sra right OP_5D OPE4_2 "shift right arith , set icc")
; Add and subtract with carry
;
(define-pmacro (int-arith-x-r-r name operation op ope comment)
(dni name
(comment)
((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1)
(FR400-MAJOR I-1) (FR450-MAJOR I-1))
(.str name "$pack $GRi,$GRj,$GRk,$ICCi_1")
(+ pack GRk op GRi ICCi_1 ope GRj)
(set GRk ((.sym operation c) GRi GRj (cbit ICCi_1)))
((fr400 (unit u-integer)) (fr450 (unit u-integer))
(fr500 (unit u-integer)) (fr550 (unit u-integer)))
)
)
(int-arith-x-r-r addx add OP_00 OPE2_02 "Add reg/reg, with carry")
(int-arith-x-r-r subx sub OP_00 OPE2_06 "Sub reg/reg, with carry")
(define-pmacro (int-arith-x-cc-r-r name operation op ope comment)
(dni name
(comment)
((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1)
(FR400-MAJOR I-1) (FR450-MAJOR I-1))
(.str name "$pack $GRi,$GRj,$GRk,$ICCi_1")
(+ pack GRk op GRi ICCi_1 ope GRj)
(sequence ((WI tmp) (QI cc))
(set cc ICCi_1)
(set tmp ((.sym operation c) GRi GRj (cbit cc)))
(set-v cc ((.sym operation -oflag) GRi GRj (cbit cc)))
(set-c cc ((.sym operation -cflag) GRi GRj (cbit cc)))
(set-z-and-n cc tmp)
(set GRk tmp)
(set ICCi_1 cc))
((fr400 (unit u-integer)) (fr450 (unit u-integer))
(fr500 (unit u-integer)) (fr550 (unit u-integer)))
)
)
(int-arith-x-cc-r-r addxcc add OP_00 OPE2_03 "Add reg/reg, use/set carry")
(int-arith-x-cc-r-r subxcc sub OP_00 OPE2_07 "Sub reg/reg, use/set carry")
; Add and subtract with saturation
;
(define-pmacro (int-arith-ss-r-r name operation op ope comment)
(dni name
(comment)
((UNIT IALL) (MACH fr400,fr450)
(FR400-MAJOR I-1) (FR450-MAJOR I-1) AUDIO)
(.str name "$pack $GRi,$GRj,$GRk")
(+ pack GRk op GRi ope GRj)
(sequence ()
(set GRk (operation GRi GRj))
(if ((.sym operation -oflag) GRi GRj (const 0))
; Overflow, saturate.
; Sign of result will be
; same as sign of first operand.
(set GRk
(cond SI
((gt GRi 0) (const #x7fffffff))
((lt GRi 0) (const #x80000000))
(else (const 0)))))
)
((fr400 (unit u-integer)) (fr450 (unit u-integer)))
)
)
(int-arith-ss-r-r addss add OP_46 OPE1_00 "add reg/reg, with saturation")
(int-arith-ss-r-r subss sub OP_46 OPE1_01 "sub reg/reg, with saturation")
; Format: INT, Logic, Shift r-simm
;
(define-pmacro (int-logic-r-simm name operation op comment)
(dni name
(comment)
((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1)
(FR400-MAJOR I-1) (FR450-MAJOR I-1))
(.str name "$pack $GRi,$s12,$GRk")
(+ pack GRk op GRi s12)
(set GRk (operation GRi s12))
((fr400 (unit u-integer)) (fr450 (unit u-integer))
(fr500 (unit u-integer)) (fr550 (unit u-integer)))
)
)
(int-logic-r-simm addi add OP_10 "add reg/immed")
(int-logic-r-simm subi sub OP_14 "sub reg/immed")
(int-logic-r-simm andi and OP_20 "and reg/immed")
(int-logic-r-simm ori or OP_22 "or reg/immed")
(int-logic-r-simm xori xor OP_24 "xor reg/immed")
(dni sdivi
"signed division reg/immed"
((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2)
(FR400-MAJOR I-1) (FR450-MAJOR I-1))
"sdivi$pack $GRi,$s12,$GRk"
(+ pack GRk OP_1E GRi s12)
(sequence ()
(c-call VOID "@cpu@_signed_integer_divide"
GRi s12 (index-of GRk) 0)
(clobber GRk))
((fr400 (unit u-idiv)) (fr450 (unit u-idiv))
(fr500 (unit u-idiv)) (fr550 (unit u-idiv)))
)
(dni nsdivi
"non excepting signed division reg/immed"
((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2) NON-EXCEPTING
(MACH simple,tomcat,fr500,fr550,frv))
"nsdivi$pack $GRi,$s12,$GRk"
(+ pack GRk OP_2E GRi s12)
(sequence ()
(c-call VOID "@cpu@_signed_integer_divide"
GRi s12 (index-of GRk) 1)
(clobber GRk))
((fr500 (unit u-idiv)) (fr550 (unit u-idiv)))
)
(dni udivi
"unsigned division reg/immed"
((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2)
(FR400-MAJOR I-1) (FR450-MAJOR I-1))
"udivi$pack $GRi,$s12,$GRk"
(+ pack GRk OP_1F GRi s12)
(sequence ()
(c-call VOID "@cpu@_unsigned_integer_divide"
GRi s12 (index-of GRk) 0)
(clobber GRk))
((fr400 (unit u-idiv)) (fr450 (unit u-idiv))
(fr500 (unit u-idiv)) (fr550 (unit u-idiv)))
)
(dni nudivi
"non excepting unsigned division reg/immed"
((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2) NON-EXCEPTING
(MACH simple,tomcat,fr500,fr550,frv))
"nudivi$pack $GRi,$s12,$GRk"
(+ pack GRk OP_2F GRi s12)
(sequence ()
(c-call VOID "@cpu@_unsigned_integer_divide"
GRi s12 (index-of GRk) 1)
(clobber GRk))
((fr500 (unit u-idiv)) (fr550 (unit u-idiv)))
)
(define-pmacro (multiply-r-simm name signop op comment)
(dni name
(comment)
((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2)
(FR400-MAJOR I-1) (FR450-MAJOR I-1))
(.str name "$pack $GRi,$s12,$GRdoublek")
(+ pack GRdoublek op GRi s12)
(set GRdoublek (mul DI (signop DI GRi) (signop DI s12)))
((fr400 (unit u-imul)) (fr450 (unit u-imul))
(fr500 (unit u-imul)) (fr550 (unit u-imul)))
)
)
(multiply-r-simm smuli ext OP_18 "signed multiply reg/immed")
(multiply-r-simm umuli zext OP_1A "unsigned multiply reg/immed")
(define-pmacro (int-shift-r-simm name op comment)
(dni (.sym name i)
(comment)
((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1)
(FR400-MAJOR I-1) (FR450-MAJOR I-1))
(.str (.sym name i) "$pack $GRi,$s12,$GRk")
(+ pack GRk op GRi s12)
(set GRk (name GRi (and s12 #x1f)))
((fr400 (unit u-integer)) (fr450 (unit u-integer))
(fr500 (unit u-integer)) (fr550 (unit u-integer)))
)
)
(int-shift-r-simm sll OP_28 "shift left logical reg/immed")
(int-shift-r-simm srl OP_2A "shift right logical reg/immed")
(int-shift-r-simm sra OP_2C "shift right arith reg/immed")
(dni scani
"scan immediate"
((UNIT SCAN) (FR500-MAJOR I-1) (FR550-MAJOR I-1)
(FR400-MAJOR I-1) (FR450-MAJOR I-1))
"scani$pack $GRi,$s12,$GRk"
(+ pack GRk OP_47 GRi s12)
(scan-semantics GRi s12 GRk)
((fr400 (unit u-integer)) (fr450 (unit u-integer))
(fr500 (unit u-integer)) (fr550 (unit u-integer)))
)
; Format: INT, Logic, Shift cc r-simm
;
(define-pmacro (int-arith-cc-r-simm name operation op comment)
(dni name
(comment)
((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1)
(FR400-MAJOR I-1) (FR450-MAJOR I-1))
(.str name "$pack $GRi,$s10,$GRk,$ICCi_1")
(+ pack GRk op GRi ICCi_1 s10)
(sequence ((BI tmp) (QI cc) (SI result))
(set cc ICCi_1)
(set tmp ((.sym operation -oflag) GRi s10 (const 0)))
(set-v cc tmp)
(set tmp ((.sym operation -cflag) GRi s10 (const 0)))
(set-c cc tmp)
(set result (operation GRi s10))
(set-z-and-n cc result)
(set GRk result)
(set ICCi_1 cc))
((fr400 (unit u-integer)) (fr450 (unit u-integer))
(fr500 (unit u-integer)) (fr550 (unit u-integer)))
)
)
(int-arith-cc-r-simm addicc add OP_11 "add reg/immed, set icc")
(int-arith-cc-r-simm subicc sub OP_15 "sub reg/immed, set icc")
(define-pmacro (int-logic-cc-r-simm name op comment)
(dni (.sym name icc)
(comment)
((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1)
(FR400-MAJOR I-1) (FR450-MAJOR I-1))
(.str (.sym name icc) "$pack $GRi,$s10,$GRk,$ICCi_1")
(+ pack GRk op GRi ICCi_1 s10)
(sequence ((SI tmp))
(set tmp (name GRi s10))
(set GRk tmp)
(set-z-and-n ICCi_1 tmp))
((fr400 (unit u-integer)) (fr450 (unit u-integer))
(fr500 (unit u-integer)) (fr550 (unit u-integer)))
)
)
(int-logic-cc-r-simm and OP_21 "and reg/immed, set icc")
(int-logic-cc-r-simm or OP_23 "or reg/immed, set icc")
(int-logic-cc-r-simm xor OP_25 "xor reg/immed, set icc")
(define-pmacro (multiply-cc-r-simm name signop op comment)
(dni name
(comment)
((UNIT MULT-DIV) (FR500-MAJOR I-1) (FR550-MAJOR I-2)
(FR400-MAJOR I-1) (FR450-MAJOR I-1))
(.str name "$pack $GRi,$s10,$GRdoublek,$ICCi_1")
(+ pack GRdoublek op GRi ICCi_1 s10)
(multiply-cc-semantics signop GRi s10 GRdoublek ICCi_1)
((fr400 (unit u-imul)) (fr450 (unit u-imul))
(fr500 (unit u-imul)) (fr550 (unit u-imul)))
)
)
(multiply-cc-r-simm smulicc ext OP_19 "signed multiply reg/immed")
(multiply-cc-r-simm umulicc zext OP_1B "unsigned multiply reg/immed")
(define-pmacro (int-shift-cc-r-simm name l-r op comment)
(dni (.sym name icc)
(comment)
((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1)
(FR400-MAJOR I-1) (FR450-MAJOR I-1))
(.str (.sym name icc) "$pack $GRi,$s10,$GRk,$ICCi_1")
(+ pack GRk op GRi ICCi_1 s10)
(sequence ((WI shift) (SI tmp) (QI cc))
(set shift (and s10 #x1f))
(set cc (c-call QI (.str "@cpu@_set_icc_for_shift_" l-r)
GRi shift ICCi_1))
(set tmp (name GRi shift))
(set GRk tmp)
(set-z-and-n cc tmp)
(set ICCi_1 cc))
((fr400 (unit u-integer)) (fr450 (unit u-integer))
(fr500 (unit u-integer)) (fr550 (unit u-integer)))
)
)
(int-shift-cc-r-simm sll left OP_29 "shift left logical reg/immed, set icc")
(int-shift-cc-r-simm srl right OP_2B "shift right logical reg/immed, set icc")
(int-shift-cc-r-simm sra right OP_2D "shift right arith reg/immed, set icc")
(define-pmacro (int-arith-x-r-simm name operation op comment)
(dni name
(comment)
((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1)
(FR400-MAJOR I-1) (FR450-MAJOR I-1))
(.str name "$pack $GRi,$s10,$GRk,$ICCi_1")
(+ pack GRk op GRi ICCi_1 s10)
(set GRk ((.sym operation c) GRi s10 (cbit ICCi_1)))
((fr400 (unit u-integer)) (fr450 (unit u-integer))
(fr500 (unit u-integer)) (fr550 (unit u-integer)))
)
)
(int-arith-x-r-simm addxi add OP_12 "Add reg/immed, with carry")
(int-arith-x-r-simm subxi sub OP_16 "Sub reg/immed, with carry")
(define-pmacro (int-arith-x-cc-r-simm name operation op comment)
(dni name
(comment)
((UNIT IALL) (FR500-MAJOR I-1) (FR550-MAJOR I-1)
(FR400-MAJOR I-1) (FR450-MAJOR I-1))
(.str name "$pack $GRi,$s10,$GRk,$ICCi_1")
(+ pack GRk op GRi ICCi_1 s10)
(sequence ((WI tmp) (QI cc))
(set cc ICCi_1)
(set tmp ((.sym operation c) GRi s10 (cbit cc)))
(set-v cc ((.sym operation -oflag) GRi s10 (cbit cc)))
(set-c cc ((.sym operation -cflag) GRi s10 (cbit cc)))
(set-z-and-n cc tmp)
(set GRk tmp)
(set ICCi_1 cc))
((fr400 (unit u-integer)) (fr450 (unit u-integer))
(fr500 (unit u-integer)) (fr550 (unit u-integer)))
)
)
(int-arith-x-cc-r-simm addxicc add OP_13 "Add reg/immed, with carry")
(int-arith-x-cc-r-simm subxicc sub OP_17 "Sub reg/immed, with carry")
; Byte compare insns
(dni cmpb
"Compare bytes"