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gnu / binutils-gdb / 4076f962e8cd73219dfd48a6f682df1ab391c48c / . / gdb / i386-tdep.c
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/* Intel 386 target-dependent stuff.
Copyright (C) 1988-2024 Free Software Foundation, Inc.
This file is part of GDB.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>. */
#include "extract-store-integer.h"
#include "opcode/i386.h"
#include "arch-utils.h"
#include "command.h"
#include "dummy-frame.h"
#include "dwarf2/frame.h"
#include "frame.h"
#include "frame-base.h"
#include "frame-unwind.h"
#include "inferior.h"
#include "infrun.h"
#include "cli/cli-cmds.h"
#include "gdbcore.h"
#include "gdbtypes.h"
#include "objfiles.h"
#include "osabi.h"
#include "regcache.h"
#include "reggroups.h"
#include "regset.h"
#include "symfile.h"
#include "symtab.h"
#include "target.h"
#include "target-float.h"
#include "value.h"
#include "dis-asm.h"
#include "disasm.h"
#include "remote.h"
#include "i386-tdep.h"
#include "i387-tdep.h"
#include "gdbsupport/x86-xstate.h"
#include "x86-tdep.h"
#include "expop.h"
#include "record.h"
#include "record-full.h"
#include "target-descriptions.h"
#include "arch/i386.h"
#include "ax.h"
#include "ax-gdb.h"
#include "stap-probe.h"
#include "user-regs.h"
#include "cli/cli-utils.h"
#include "expression.h"
#include "parser-defs.h"
#include <ctype.h>
#include <algorithm>
#include <unordered_set>
#include "producer.h"
#include "infcall.h"
#include "maint.h"
/* Register names. */
static const char * const i386_register_names[] =
{
"eax", "ecx", "edx", "ebx",
"esp", "ebp", "esi", "edi",
"eip", "eflags", "cs", "ss",
"ds", "es", "fs", "gs",
"st0", "st1", "st2", "st3",
"st4", "st5", "st6", "st7",
"fctrl", "fstat", "ftag", "fiseg",
"fioff", "foseg", "fooff", "fop",
"xmm0", "xmm1", "xmm2", "xmm3",
"xmm4", "xmm5", "xmm6", "xmm7",
"mxcsr"
};
static const char * const i386_zmm_names[] =
{
"zmm0", "zmm1", "zmm2", "zmm3",
"zmm4", "zmm5", "zmm6", "zmm7"
};
static const char * const i386_zmmh_names[] =
{
"zmm0h", "zmm1h", "zmm2h", "zmm3h",
"zmm4h", "zmm5h", "zmm6h", "zmm7h"
};
static const char * const i386_k_names[] =
{
"k0", "k1", "k2", "k3",
"k4", "k5", "k6", "k7"
};
static const char * const i386_ymm_names[] =
{
"ymm0", "ymm1", "ymm2", "ymm3",
"ymm4", "ymm5", "ymm6", "ymm7",
};
static const char * const i386_ymmh_names[] =
{
"ymm0h", "ymm1h", "ymm2h", "ymm3h",
"ymm4h", "ymm5h", "ymm6h", "ymm7h",
};
static const char * const i386_mpx_names[] =
{
"bnd0raw", "bnd1raw", "bnd2raw", "bnd3raw", "bndcfgu", "bndstatus"
};
static const char * const i386_pkeys_names[] =
{
"pkru"
};
/* Register names for MPX pseudo-registers. */
static const char * const i386_bnd_names[] =
{
"bnd0", "bnd1", "bnd2", "bnd3"
};
/* Register names for MMX pseudo-registers. */
static const char * const i386_mmx_names[] =
{
"mm0", "mm1", "mm2", "mm3",
"mm4", "mm5", "mm6", "mm7"
};
/* Register names for byte pseudo-registers. */
static const char * const i386_byte_names[] =
{
"al", "cl", "dl", "bl",
"ah", "ch", "dh", "bh"
};
/* Register names for word pseudo-registers. */
static const char * const i386_word_names[] =
{
"ax", "cx", "dx", "bx",
"", "bp", "si", "di"
};
/* Constant used for reading/writing pseudo registers. In 64-bit mode, we have
16 lower ZMM regs that extend corresponding xmm/ymm registers. In addition,
we have 16 upper ZMM regs that have to be handled differently. */
const int num_lower_zmm_regs = 16;
/* MMX register? */
static int
i386_mmx_regnum_p (struct gdbarch *gdbarch, int regnum)
{
i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch);
int mm0_regnum = tdep->mm0_regnum;
if (mm0_regnum < 0)
return 0;
regnum -= mm0_regnum;
return regnum >= 0 && regnum < tdep->num_mmx_regs;
}
/* Byte register? */
int
i386_byte_regnum_p (struct gdbarch *gdbarch, int regnum)
{
i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch);
regnum -= tdep->al_regnum;
return regnum >= 0 && regnum < tdep->num_byte_regs;
}
/* Word register? */
int
i386_word_regnum_p (struct gdbarch *gdbarch, int regnum)
{
i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch);
regnum -= tdep->ax_regnum;
return regnum >= 0 && regnum < tdep->num_word_regs;
}
/* Dword register? */
int
i386_dword_regnum_p (struct gdbarch *gdbarch, int regnum)
{
i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch);
int eax_regnum = tdep->eax_regnum;
if (eax_regnum < 0)
return 0;
regnum -= eax_regnum;
return regnum >= 0 && regnum < tdep->num_dword_regs;
}
/* AVX512 register? */
int
i386_zmmh_regnum_p (struct gdbarch *gdbarch, int regnum)
{
i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch);
int zmm0h_regnum = tdep->zmm0h_regnum;
if (zmm0h_regnum < 0)
return 0;
regnum -= zmm0h_regnum;
return regnum >= 0 && regnum < tdep->num_zmm_regs;
}
int
i386_zmm_regnum_p (struct gdbarch *gdbarch, int regnum)
{
i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch);
int zmm0_regnum = tdep->zmm0_regnum;
if (zmm0_regnum < 0)
return 0;
regnum -= zmm0_regnum;
return regnum >= 0 && regnum < tdep->num_zmm_regs;
}
int
i386_k_regnum_p (struct gdbarch *gdbarch, int regnum)
{
i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch);
int k0_regnum = tdep->k0_regnum;
if (k0_regnum < 0)
return 0;
regnum -= k0_regnum;
return regnum >= 0 && regnum < I387_NUM_K_REGS;
}
static int
i386_ymmh_regnum_p (struct gdbarch *gdbarch, int regnum)
{
i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch);
int ymm0h_regnum = tdep->ymm0h_regnum;
if (ymm0h_regnum < 0)
return 0;
regnum -= ymm0h_regnum;
return regnum >= 0 && regnum < tdep->num_ymm_regs;
}
/* AVX register? */
int
i386_ymm_regnum_p (struct gdbarch *gdbarch, int regnum)
{
i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch);
int ymm0_regnum = tdep->ymm0_regnum;
if (ymm0_regnum < 0)
return 0;
regnum -= ymm0_regnum;
return regnum >= 0 && regnum < tdep->num_ymm_regs;
}
static int
i386_ymmh_avx512_regnum_p (struct gdbarch *gdbarch, int regnum)
{
i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch);
int ymm16h_regnum = tdep->ymm16h_regnum;
if (ymm16h_regnum < 0)
return 0;
regnum -= ymm16h_regnum;
return regnum >= 0 && regnum < tdep->num_ymm_avx512_regs;
}
int
i386_ymm_avx512_regnum_p (struct gdbarch *gdbarch, int regnum)
{
i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch);
int ymm16_regnum = tdep->ymm16_regnum;
if (ymm16_regnum < 0)
return 0;
regnum -= ymm16_regnum;
return regnum >= 0 && regnum < tdep->num_ymm_avx512_regs;
}
/* BND register? */
int
i386_bnd_regnum_p (struct gdbarch *gdbarch, int regnum)
{
i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch);
int bnd0_regnum = tdep->bnd0_regnum;
if (bnd0_regnum < 0)
return 0;
regnum -= bnd0_regnum;
return regnum >= 0 && regnum < I387_NUM_BND_REGS;
}
/* SSE register? */
int
i386_xmm_regnum_p (struct gdbarch *gdbarch, int regnum)
{
i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch);
int num_xmm_regs = I387_NUM_XMM_REGS (tdep);
if (num_xmm_regs == 0)
return 0;
regnum -= I387_XMM0_REGNUM (tdep);
return regnum >= 0 && regnum < num_xmm_regs;
}
/* XMM_512 register? */
int
i386_xmm_avx512_regnum_p (struct gdbarch *gdbarch, int regnum)
{
i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch);
int num_xmm_avx512_regs = I387_NUM_XMM_AVX512_REGS (tdep);
if (num_xmm_avx512_regs == 0)
return 0;
regnum -= I387_XMM16_REGNUM (tdep);
return regnum >= 0 && regnum < num_xmm_avx512_regs;
}
static int
i386_mxcsr_regnum_p (struct gdbarch *gdbarch, int regnum)
{
i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch);
if (I387_NUM_XMM_REGS (tdep) == 0)
return 0;
return (regnum == I387_MXCSR_REGNUM (tdep));
}
/* FP register? */
int
i386_fp_regnum_p (struct gdbarch *gdbarch, int regnum)
{
i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch);
if (I387_ST0_REGNUM (tdep) < 0)
return 0;
return (I387_ST0_REGNUM (tdep) <= regnum
&& regnum < I387_FCTRL_REGNUM (tdep));
}
int
i386_fpc_regnum_p (struct gdbarch *gdbarch, int regnum)
{
i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch);
if (I387_ST0_REGNUM (tdep) < 0)
return 0;
return (I387_FCTRL_REGNUM (tdep) <= regnum
&& regnum < I387_XMM0_REGNUM (tdep));
}
/* BNDr (raw) register? */
static int
i386_bndr_regnum_p (struct gdbarch *gdbarch, int regnum)
{
i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch);
if (I387_BND0R_REGNUM (tdep) < 0)
return 0;
regnum -= tdep->bnd0r_regnum;
return regnum >= 0 && regnum < I387_NUM_BND_REGS;
}
/* BND control register? */
static int
i386_mpx_ctrl_regnum_p (struct gdbarch *gdbarch, int regnum)
{
i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch);
if (I387_BNDCFGU_REGNUM (tdep) < 0)
return 0;
regnum -= I387_BNDCFGU_REGNUM (tdep);
return regnum >= 0 && regnum < I387_NUM_MPX_CTRL_REGS;
}
/* PKRU register? */
bool
i386_pkru_regnum_p (struct gdbarch *gdbarch, int regnum)
{
i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch);
int pkru_regnum = tdep->pkru_regnum;
if (pkru_regnum < 0)
return false;
regnum -= pkru_regnum;
return regnum >= 0 && regnum < I387_NUM_PKEYS_REGS;
}
/* Return the name of register REGNUM, or the empty string if it is
an anonymous register. */
static const char *
i386_register_name (struct gdbarch *gdbarch, int regnum)
{
/* Hide the upper YMM registers. */
if (i386_ymmh_regnum_p (gdbarch, regnum))
return "";
/* Hide the upper YMM16-31 registers. */
if (i386_ymmh_avx512_regnum_p (gdbarch, regnum))
return "";
/* Hide the upper ZMM registers. */
if (i386_zmmh_regnum_p (gdbarch, regnum))
return "";
return tdesc_register_name (gdbarch, regnum);
}
/* Return the name of register REGNUM. */
const char *
i386_pseudo_register_name (struct gdbarch *gdbarch, int regnum)
{
i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch);
if (i386_bnd_regnum_p (gdbarch, regnum))
return i386_bnd_names[regnum - tdep->bnd0_regnum];
if (i386_mmx_regnum_p (gdbarch, regnum))
return i386_mmx_names[regnum - I387_MM0_REGNUM (tdep)];
else if (i386_ymm_regnum_p (gdbarch, regnum))
return i386_ymm_names[regnum - tdep->ymm0_regnum];
else if (i386_zmm_regnum_p (gdbarch, regnum))
return i386_zmm_names[regnum - tdep->zmm0_regnum];
else if (i386_byte_regnum_p (gdbarch, regnum))
return i386_byte_names[regnum - tdep->al_regnum];
else if (i386_word_regnum_p (gdbarch, regnum))
return i386_word_names[regnum - tdep->ax_regnum];
internal_error (_("invalid regnum"));
}
/* Convert a dbx register number REG to the appropriate register
number used by GDB. */
static int
i386_dbx_reg_to_regnum (struct gdbarch *gdbarch, int reg)
{
i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch);
/* This implements what GCC calls the "default" register map
(dbx_register_map[]). */
if (reg >= 0 && reg <= 7)
{
/* General-purpose registers. The debug info calls %ebp
register 4, and %esp register 5. */
if (reg == 4)
return 5;
else if (reg == 5)
return 4;
else return reg;
}
else if (reg >= 12 && reg <= 19)
{
/* Floating-point registers. */
return reg - 12 + I387_ST0_REGNUM (tdep);
}
else if (reg >= 21 && reg <= 28)
{
/* SSE registers. */
int ymm0_regnum = tdep->ymm0_regnum;
if (ymm0_regnum >= 0
&& i386_xmm_regnum_p (gdbarch, reg))
return reg - 21 + ymm0_regnum;
else
return reg - 21 + I387_XMM0_REGNUM (tdep);
}
else if (reg >= 29 && reg <= 36)
{
/* MMX registers. */
return reg - 29 + I387_MM0_REGNUM (tdep);
}
/* This will hopefully provoke a warning. */
return gdbarch_num_cooked_regs (gdbarch);
}
/* Convert SVR4 DWARF register number REG to the appropriate register number
used by GDB. */
static int
i386_svr4_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int reg)
{
i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch);
/* This implements the GCC register map that tries to be compatible
with the SVR4 C compiler for DWARF (svr4_dbx_register_map[]). */
/* The SVR4 register numbering includes %eip and %eflags, and
numbers the floating point registers differently. */
if (reg >= 0 && reg <= 9)
{
/* General-purpose registers. */
return reg;
}
else if (reg >= 11 && reg <= 18)
{
/* Floating-point registers. */
return reg - 11 + I387_ST0_REGNUM (tdep);
}
else if (reg >= 21 && reg <= 36)
{
/* The SSE and MMX registers have the same numbers as with dbx. */
return i386_dbx_reg_to_regnum (gdbarch, reg);
}
switch (reg)
{
case 37: return I387_FCTRL_REGNUM (tdep);
case 38: return I387_FSTAT_REGNUM (tdep);
case 39: return I387_MXCSR_REGNUM (tdep);
case 40: return I386_ES_REGNUM;
case 41: return I386_CS_REGNUM;
case 42: return I386_SS_REGNUM;
case 43: return I386_DS_REGNUM;
case 44: return I386_FS_REGNUM;
case 45: return I386_GS_REGNUM;
}
return -1;
}
/* Wrapper on i386_svr4_dwarf_reg_to_regnum to return
num_regs + num_pseudo_regs for other debug formats. */
int
i386_svr4_reg_to_regnum (struct gdbarch *gdbarch, int reg)
{
int regnum = i386_svr4_dwarf_reg_to_regnum (gdbarch, reg);
if (regnum == -1)
return gdbarch_num_cooked_regs (gdbarch);
return regnum;
}
/* This is the variable that is set with "set disassembly-flavor", and
its legitimate values. */
static const char att_flavor[] = "att";
static const char intel_flavor[] = "intel";
static const char *const valid_flavors[] =
{
att_flavor,
intel_flavor,
NULL
};
static const char *disassembly_flavor = att_flavor;
/* Use the program counter to determine the contents and size of a
breakpoint instruction. Return a pointer to a string of bytes that
encode a breakpoint instruction, store the length of the string in
*LEN and optionally adjust *PC to point to the correct memory
location for inserting the breakpoint.
On the i386 we have a single breakpoint that fits in a single byte
and can be inserted anywhere.
This function is 64-bit safe. */
constexpr gdb_byte i386_break_insn[] = { 0xcc }; /* int 3 */
typedef BP_MANIPULATION (i386_break_insn) i386_breakpoint;
/* Displaced instruction handling. */
/* Skip the legacy instruction prefixes in INSN.
Not all prefixes are valid for any particular insn
but we needn't care, the insn will fault if it's invalid.
The result is a pointer to the first opcode byte,
or NULL if we run off the end of the buffer. */
static gdb_byte *
i386_skip_prefixes (gdb_byte *insn, size_t max_len)
{
gdb_byte *end = insn + max_len;
while (insn < end)
{
switch (*insn)
{
case DATA_PREFIX_OPCODE:
case ADDR_PREFIX_OPCODE:
case CS_PREFIX_OPCODE:
case DS_PREFIX_OPCODE:
case ES_PREFIX_OPCODE:
case FS_PREFIX_OPCODE:
case GS_PREFIX_OPCODE:
case SS_PREFIX_OPCODE:
case LOCK_PREFIX_OPCODE:
case REPE_PREFIX_OPCODE:
case REPNE_PREFIX_OPCODE:
++insn;
continue;
default:
return insn;
}
}
return NULL;
}
static int
i386_absolute_jmp_p (const gdb_byte *insn)
{
/* jmp far (absolute address in operand). */
if (insn[0] == 0xea)
return 1;
if (insn[0] == 0xff)
{
/* jump near, absolute indirect (/4). */
if ((insn[1] & 0x38) == 0x20)
return 1;
/* jump far, absolute indirect (/5). */
if ((insn[1] & 0x38) == 0x28)
return 1;
}
return 0;
}
/* Return non-zero if INSN is a jump, zero otherwise. */
static int
i386_jmp_p (const gdb_byte *insn)
{
/* jump short, relative. */
if (insn[0] == 0xeb)
return 1;
/* jump near, relative. */
if (insn[0] == 0xe9)
return 1;
return i386_absolute_jmp_p (insn);
}
static int
i386_absolute_call_p (const gdb_byte *insn)
{
/* call far, absolute. */
if (insn[0] == 0x9a)
return 1;
if (insn[0] == 0xff)
{
/* Call near, absolute indirect (/2). */
if ((insn[1] & 0x38) == 0x10)
return 1;
/* Call far, absolute indirect (/3). */
if ((insn[1] & 0x38) == 0x18)
return 1;
}
return 0;
}
static int
i386_ret_p (const gdb_byte *insn)
{
switch (insn[0])
{
case 0xc2: /* ret near, pop N bytes. */
case 0xc3: /* ret near */
case 0xca: /* ret far, pop N bytes. */
case 0xcb: /* ret far */
case 0xcf: /* iret */
return 1;
default:
return 0;
}
}
static int
i386_call_p (const gdb_byte *insn)
{
if (i386_absolute_call_p (insn))
return 1;
/* call near, relative. */
if (insn[0] == 0xe8)
return 1;
return 0;
}
/* Return non-zero if INSN is a system call, and set *LENGTHP to its
length in bytes. Otherwise, return zero. */
static int
i386_syscall_p (const gdb_byte *insn, int *lengthp)
{
/* Is it 'int $0x80'? */
if ((insn[0] == 0xcd && insn[1] == 0x80)
/* Or is it 'sysenter'? */
|| (insn[0] == 0x0f && insn[1] == 0x34)
/* Or is it 'syscall'? */
|| (insn[0] == 0x0f && insn[1] == 0x05))
{
*lengthp = 2;
return 1;
}
return 0;
}
/* The gdbarch insn_is_call method. */
static int
i386_insn_is_call (struct gdbarch *gdbarch, CORE_ADDR addr)
{
gdb_byte buf[I386_MAX_INSN_LEN], *insn;
read_code (addr, buf, I386_MAX_INSN_LEN);
insn = i386_skip_prefixes (buf, I386_MAX_INSN_LEN);
return i386_call_p (insn);
}
/* The gdbarch insn_is_ret method. */
static int
i386_insn_is_ret (struct gdbarch *gdbarch, CORE_ADDR addr)
{
gdb_byte buf[I386_MAX_INSN_LEN], *insn;
read_code (addr, buf, I386_MAX_INSN_LEN);
insn = i386_skip_prefixes (buf, I386_MAX_INSN_LEN);
return i386_ret_p (insn);
}
/* The gdbarch insn_is_jump method. */
static int
i386_insn_is_jump (struct gdbarch *gdbarch, CORE_ADDR addr)
{
gdb_byte buf[I386_MAX_INSN_LEN], *insn;
read_code (addr, buf, I386_MAX_INSN_LEN);
insn = i386_skip_prefixes (buf, I386_MAX_INSN_LEN);
return i386_jmp_p (insn);
}
/* Some kernels may run one past a syscall insn, so we have to cope. */
displaced_step_copy_insn_closure_up
i386_displaced_step_copy_insn (struct gdbarch *gdbarch,
CORE_ADDR from, CORE_ADDR to,
struct regcache *regs)
{
size_t len = gdbarch_max_insn_length (gdbarch);
std::unique_ptr<i386_displaced_step_copy_insn_closure> closure
(new i386_displaced_step_copy_insn_closure (len));
gdb_byte *buf = closure->buf.data ();
read_memory (from, buf, len);
/* GDB may get control back after the insn after the syscall.
Presumably this is a kernel bug.
If this is a syscall, make sure there's a nop afterwards. */
{
int syscall_length;
gdb_byte *insn;
insn = i386_skip_prefixes (buf, len);
if (insn != NULL && i386_syscall_p (insn, &syscall_length))
insn[syscall_length] = NOP_OPCODE;
}
write_memory (to, buf, len);
displaced_debug_printf ("%s->%s: %s",
paddress (gdbarch, from), paddress (gdbarch, to),
bytes_to_string (buf, len).c_str ());
/* This is a work around for a problem with g++ 4.8. */
return displaced_step_copy_insn_closure_up (closure.release ());
}
/* Fix up the state of registers and memory after having single-stepped
a displaced instruction. */
void
i386_displaced_step_fixup (struct gdbarch *gdbarch,
struct displaced_step_copy_insn_closure *closure_,
CORE_ADDR from, CORE_ADDR to,
struct regcache *regs, bool completed_p)
{
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
/* The offset we applied to the instruction's address.
This could well be negative (when viewed as a signed 32-bit
value), but ULONGEST won't reflect that, so take care when
applying it. */
ULONGEST insn_offset = to - from;
i386_displaced_step_copy_insn_closure *closure
= (i386_displaced_step_copy_insn_closure *) closure_;
gdb_byte *insn = closure->buf.data ();
/* The start of the insn, needed in case we see some prefixes. */
gdb_byte *insn_start = insn;
displaced_debug_printf ("fixup (%s, %s), insn = 0x%02x 0x%02x ...",
paddress (gdbarch, from), paddress (gdbarch, to),
insn[0], insn[1]);
/* The list of issues to contend with here is taken from
resume_execution in arch/i386/kernel/kprobes.c, Linux 2.6.20.
Yay for Free Software! */
/* Relocate the %eip, if necessary. */
/* The instruction recognizers we use assume any leading prefixes
have been skipped. */
{
/* This is the size of the buffer in closure. */
size_t max_insn_len = gdbarch_max_insn_length (gdbarch);
gdb_byte *opcode = i386_skip_prefixes (insn, max_insn_len);
/* If there are too many prefixes, just ignore the insn.
It will fault when run. */
if (opcode != NULL)
insn = opcode;
}
/* Except in the case of absolute or indirect jump or call
instructions, or a return instruction, the new eip is relative to
the displaced instruction; make it relative. Well, signal
handler returns don't need relocation either, but we use the
value of %eip to recognize those; see below. */
if (!completed_p
|| (!i386_absolute_jmp_p (insn)
&& !i386_absolute_call_p (insn)
&& !i386_ret_p (insn)))
{
int insn_len;
CORE_ADDR pc = regcache_read_pc (regs);
/* A signal trampoline system call changes the %eip, resuming
execution of the main program after the signal handler has
returned. That makes them like 'return' instructions; we
shouldn't relocate %eip.
But most system calls don't, and we do need to relocate %eip.
Our heuristic for distinguishing these cases: if stepping
over the system call instruction left control directly after
the instruction, the we relocate --- control almost certainly
doesn't belong in the displaced copy. Otherwise, we assume
the instruction has put control where it belongs, and leave
it unrelocated. Goodness help us if there are PC-relative
system calls. */
if (i386_syscall_p (insn, &insn_len)
&& pc != to + (insn - insn_start) + insn_len
/* GDB can get control back after the insn after the syscall.
Presumably this is a kernel bug.
i386_displaced_step_copy_insn ensures it's a nop,
we add one to the length for it. */
&& pc != to + (insn - insn_start) + insn_len + 1)
displaced_debug_printf ("syscall changed %%eip; not relocating");
else
{
ULONGEST eip = (pc - insn_offset) & 0xffffffffUL;
/* If we just stepped over a breakpoint insn, we don't backup
the pc on purpose; this is to match behaviour without
stepping. */
regcache_write_pc (regs, eip);
displaced_debug_printf ("relocated %%eip from %s to %s",
paddress (gdbarch, pc),
paddress (gdbarch, eip));
}
}
/* If the instruction was PUSHFL, then the TF bit will be set in the
pushed value, and should be cleared. We'll leave this for later,
since GDB already messes up the TF flag when stepping over a
pushfl. */
/* If the instruction was a call, the return address now atop the
stack is the address following the copied instruction. We need
to make it the address following the original instruction. */
if (completed_p && i386_call_p (insn))
{
ULONGEST esp;
ULONGEST retaddr;
const ULONGEST retaddr_len = 4;
regcache_cooked_read_unsigned (regs, I386_ESP_REGNUM, &esp);
retaddr = read_memory_unsigned_integer (esp, retaddr_len, byte_order);
retaddr = (retaddr - insn_offset) & 0xffffffffUL;
write_memory_unsigned_integer (esp, retaddr_len, byte_order, retaddr);
displaced_debug_printf ("relocated return addr at %s to %s",
paddress (gdbarch, esp),
paddress (gdbarch, retaddr));
}
}
static void
append_insns (CORE_ADDR *to, ULONGEST len, const gdb_byte *buf)
{
target_write_memory (*to, buf, len);
*to += len;
}
static void
i386_relocate_instruction (struct gdbarch *gdbarch,
CORE_ADDR *to, CORE_ADDR oldloc)
{
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
gdb_byte buf[I386_MAX_INSN_LEN];
int offset = 0, rel32, newrel;
int insn_length;
gdb_byte *insn = buf;
read_memory (oldloc, buf, I386_MAX_INSN_LEN);
insn_length = gdb_buffered_insn_length (gdbarch, insn,
I386_MAX_INSN_LEN, oldloc);
/* Get past the prefixes. */
insn = i386_skip_prefixes (insn, I386_MAX_INSN_LEN);
/* Adjust calls with 32-bit relative addresses as push/jump, with
the address pushed being the location where the original call in
the user program would return to. */
if (insn[0] == 0xe8)
{
gdb_byte push_buf[16];
unsigned int ret_addr;
/* Where "ret" in the original code will return to. */
ret_addr = oldloc + insn_length;
push_buf[0] = 0x68; /* pushq $... */
store_unsigned_integer (&push_buf[1], 4, byte_order, ret_addr);
/* Push the push. */
append_insns (to, 5, push_buf);
/* Convert the relative call to a relative jump. */
insn[0] = 0xe9;
/* Adjust the destination offset. */
rel32 = extract_signed_integer (insn + 1, 4, byte_order);
newrel = (oldloc - *to) + rel32;
store_signed_integer (insn + 1, 4, byte_order, newrel);
displaced_debug_printf ("adjusted insn rel32=%s at %s to rel32=%s at %s",
hex_string (rel32), paddress (gdbarch, oldloc),
hex_string (newrel), paddress (gdbarch, *to));
/* Write the adjusted jump into its displaced location. */
append_insns (to, 5, insn);
return;
}
/* Adjust jumps with 32-bit relative addresses. Calls are already
handled above. */
if (insn[0] == 0xe9)
offset = 1;
/* Adjust conditional jumps. */
else if (insn[0] == 0x0f && (insn[1] & 0xf0) == 0x80)
offset = 2;
if (offset)
{
rel32 = extract_signed_integer (insn + offset, 4, byte_order);
newrel = (oldloc - *to) + rel32;
store_signed_integer (insn + offset, 4, byte_order, newrel);
displaced_debug_printf ("adjusted insn rel32=%s at %s to rel32=%s at %s",
hex_string (rel32), paddress (gdbarch, oldloc),
hex_string (newrel), paddress (gdbarch, *to));
}
/* Write the adjusted instructions into their displaced
location. */
append_insns (to, insn_length, buf);
}
#ifdef I386_REGNO_TO_SYMMETRY
#error "The Sequent Symmetry is no longer supported."
#endif
/* According to the System V ABI, the registers %ebp, %ebx, %edi, %esi
and %esp "belong" to the calling function. Therefore these
registers should be saved if they're going to be modified. */
/* The maximum number of saved registers. This should include all
registers mentioned above, and %eip. */
#define I386_NUM_SAVED_REGS I386_NUM_GREGS
struct i386_frame_cache
{
/* Base address. */
CORE_ADDR base;
int base_p;
LONGEST sp_offset;
CORE_ADDR pc;
/* Saved registers. */
CORE_ADDR saved_regs[I386_NUM_SAVED_REGS];
CORE_ADDR saved_sp;
int saved_sp_reg;
int pc_in_eax;
/* Stack space reserved for local variables. */
long locals;
};
/* Allocate and initialize a frame cache. */
static struct i386_frame_cache *
i386_alloc_frame_cache (void)
{
struct i386_frame_cache *cache;
int i;
cache = FRAME_OBSTACK_ZALLOC (struct i386_frame_cache);
/* Base address. */
cache->base_p = 0;
cache->base = 0;
cache->sp_offset = -4;
cache->pc = 0;
/* Saved registers. We initialize these to -1 since zero is a valid
offset (that's where %ebp is supposed to be stored). */
for (i = 0; i < I386_NUM_SAVED_REGS; i++)
cache->saved_regs[i] = -1;
cache->saved_sp = 0;
cache->saved_sp_reg = -1;
cache->pc_in_eax = 0;
/* Frameless until proven otherwise. */
cache->locals = -1;
return cache;
}
/* If the instruction at PC is a jump, return the address of its
target. Otherwise, return PC. */
static CORE_ADDR
i386_follow_jump (struct gdbarch *gdbarch, CORE_ADDR pc)
{
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
gdb_byte op;
long delta = 0;
int data16 = 0;
if (target_read_code (pc, &op, 1))
return pc;
if (op == 0x66)
{
data16 = 1;
op = read_code_unsigned_integer (pc + 1, 1, byte_order);
}
switch (op)
{
case 0xe9:
/* Relative jump: if data16 == 0, disp32, else disp16. */
if (data16)
{
delta = read_memory_integer (pc + 2, 2, byte_order);
/* Include the size of the jmp instruction (including the
0x66 prefix). */
delta += 4;
}
else
{
delta = read_memory_integer (pc + 1, 4, byte_order);
/* Include the size of the jmp instruction. */
delta += 5;
}
break;
case 0xeb:
/* Relative jump, disp8 (ignore data16). */
delta = read_memory_integer (pc + data16 + 1, 1, byte_order);
delta += data16 + 2;
break;
}
return pc + delta;
}
/* Check whether PC points at a prologue for a function returning a
structure or union. If so, it updates CACHE and returns the
address of the first instruction after the code sequence that
removes the "hidden" argument from the stack or CURRENT_PC,
whichever is smaller. Otherwise, return PC. */
static CORE_ADDR
i386_analyze_struct_return (CORE_ADDR pc, CORE_ADDR current_pc,
struct i386_frame_cache *cache)
{
/* Functions that return a structure or union start with:
popl %eax 0x58
xchgl %eax, (%esp) 0x87 0x04 0x24
or xchgl %eax, 0(%esp) 0x87 0x44 0x24 0x00
(the System V compiler puts out the second `xchg' instruction,
and the assembler doesn't try to optimize it, so the 'sib' form
gets generated). This sequence is used to get the address of the
return buffer for a function that returns a structure. */
static gdb_byte proto1[3] = { 0x87, 0x04, 0x24 };
static gdb_byte proto2[4] = { 0x87, 0x44, 0x24, 0x00 };
gdb_byte buf[4];
gdb_byte op;
if (current_pc <= pc)
return pc;
if (target_read_code (pc, &op, 1))
return pc;
if (op != 0x58) /* popl %eax */
return pc;
if (target_read_code (pc + 1, buf, 4))
return pc;
if (memcmp (buf, proto1, 3) != 0 && memcmp (buf, proto2, 4) != 0)
return pc;
if (current_pc == pc)
{
cache->sp_offset += 4;
return current_pc;
}
if (current_pc == pc + 1)
{
cache->pc_in_eax = 1;
return current_pc;
}
if (buf[1] == proto1[1])
return pc + 4;
else
return pc + 5;
}
static CORE_ADDR
i386_skip_probe (CORE_ADDR pc)
{
/* A function may start with
pushl constant
call _probe
addl $4, %esp
followed by
pushl %ebp
etc. */
gdb_byte buf[8];
gdb_byte op;
if (target_read_code (pc, &op, 1))
return pc;
if (op == 0x68 || op == 0x6a)
{
int delta;
/* Skip past the `pushl' instruction; it has either a one-byte or a
four-byte operand, depending on the opcode. */
if (op == 0x68)
delta = 5;
else
delta = 2;
/* Read the following 8 bytes, which should be `call _probe' (6
bytes) followed by `addl $4,%esp' (2 bytes). */
read_memory (pc + delta, buf, sizeof (buf));
if (buf[0] == 0xe8 && buf[6] == 0xc4 && buf[7] == 0x4)
pc += delta + sizeof (buf);
}
return pc;
}
/* GCC 4.1 and later, can put code in the prologue to realign the
stack pointer. Check whether PC points to such code, and update
CACHE accordingly. Return the first instruction after the code
sequence or CURRENT_PC, whichever is smaller. If we don't
recognize the code, return PC. */
static CORE_ADDR
i386_analyze_stack_align (CORE_ADDR pc, CORE_ADDR current_pc,
struct i386_frame_cache *cache)
{
/* There are 2 code sequences to re-align stack before the frame
gets set up:
1. Use a caller-saved saved register:
leal 4(%esp), %reg
andl $-XXX, %esp
pushl -4(%reg)
2. Use a callee-saved saved register:
pushl %reg
leal 8(%esp), %reg
andl $-XXX, %esp
pushl -4(%reg)
"andl $-XXX, %esp" can be either 3 bytes or 6 bytes:
0x83 0xe4 0xf0 andl $-16, %esp
0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp
*/
gdb_byte buf[14];
int reg;
int offset, offset_and;
static int regnums[8] = {
I386_EAX_REGNUM, /* %eax */
I386_ECX_REGNUM, /* %ecx */
I386_EDX_REGNUM, /* %edx */
I386_EBX_REGNUM, /* %ebx */
I386_ESP_REGNUM, /* %esp */
I386_EBP_REGNUM, /* %ebp */
I386_ESI_REGNUM, /* %esi */
I386_EDI_REGNUM /* %edi */
};
if (target_read_code (pc, buf, sizeof buf))
return pc;
/* Check caller-saved saved register. The first instruction has
to be "leal 4(%esp), %reg". */
if (buf[0] == 0x8d && buf[2] == 0x24 && buf[3] == 0x4)
{
/* MOD must be binary 10 and R/M must be binary 100. */
if ((buf[1] & 0xc7) != 0x44)
return pc;
/* REG has register number. */
reg = (buf[1] >> 3) & 7;
offset = 4;
}
else
{
/* Check callee-saved saved register. The first instruction
has to be "pushl %reg". */
if ((buf[0] & 0xf8) != 0x50)
return pc;
/* Get register. */
reg = buf[0] & 0x7;
/* The next instruction has to be "leal 8(%esp), %reg". */
if (buf[1] != 0x8d || buf[3] != 0x24 || buf[4] != 0x8)
return pc;
/* MOD must be binary 10 and R/M must be binary 100. */
if ((buf[2] & 0xc7) != 0x44)
return pc;
/* REG has register number. Registers in pushl and leal have to
be the same. */
if (reg != ((buf[2] >> 3) & 7))
return pc;
offset = 5;
}
/* Rigister can't be %esp nor %ebp. */
if (reg == 4 || reg == 5)
return pc;
/* The next instruction has to be "andl $-XXX, %esp". */
if (buf[offset + 1] != 0xe4
|| (buf[offset] != 0x81 && buf[offset] != 0x83))
return pc;
offset_and = offset;
offset += buf[offset] == 0x81 ? 6 : 3;
/* The next instruction has to be "pushl -4(%reg)". 8bit -4 is
0xfc. REG must be binary 110 and MOD must be binary 01. */
if (buf[offset] != 0xff
|| buf[offset + 2] != 0xfc
|| (buf[offset + 1] & 0xf8) != 0x70)
return pc;
/* R/M has register. Registers in leal and pushl have to be the
same. */
if (reg != (buf[offset + 1] & 7))
return pc;
if (current_pc > pc + offset_and)
cache->saved_sp_reg = regnums[reg];
return std::min (pc + offset + 3, current_pc);
}
/* Maximum instruction length we need to handle. */
#define I386_MAX_MATCHED_INSN_LEN 6
/* Instruction description. */
struct i386_insn
{
size_t len;
gdb_byte insn[I386_MAX_MATCHED_INSN_LEN];
gdb_byte mask[I386_MAX_MATCHED_INSN_LEN];
};
/* Return whether instruction at PC matches PATTERN. */
static int
i386_match_pattern (CORE_ADDR pc, struct i386_insn pattern)
{
gdb_byte op;
if (target_read_code (pc, &op, 1))
return 0;
if ((op & pattern.mask[0]) == pattern.insn[0])
{
gdb_byte buf[I386_MAX_MATCHED_INSN_LEN - 1];
int insn_matched = 1;
size_t i;
gdb_assert (pattern.len > 1);
gdb_assert (pattern.len <= I386_MAX_MATCHED_INSN_LEN);
if (target_read_code (pc + 1, buf, pattern.len - 1))
return 0;
for (i = 1; i < pattern.len; i++)
{
if ((buf[i - 1] & pattern.mask[i]) != pattern.insn[i])
insn_matched = 0;
}
return insn_matched;
}
return 0;
}
/* Search for the instruction at PC in the list INSN_PATTERNS. Return
the first instruction description that matches. Otherwise, return
NULL. */
static struct i386_insn *
i386_match_insn (CORE_ADDR pc, struct i386_insn *insn_patterns)
{
struct i386_insn *pattern;
for (pattern = insn_patterns; pattern->len > 0; pattern++)
{
if (i386_match_pattern (pc, *pattern))
return pattern;
}
return NULL;
}
/* Return whether PC points inside a sequence of instructions that
matches INSN_PATTERNS. */
static int
i386_match_insn_block (CORE_ADDR pc, struct i386_insn *insn_patterns)
{
CORE_ADDR current_pc;
int ix, i;
struct i386_insn *insn;
insn = i386_match_insn (pc, insn_patterns);
if (insn == NULL)
return 0;
current_pc = pc;
ix = insn - insn_patterns;
for (i = ix - 1; i >= 0; i--)
{
current_pc -= insn_patterns[i].len;
if (!i386_match_pattern (current_pc, insn_patterns[i]))
return 0;
}
current_pc = pc + insn->len;
for (insn = insn_patterns + ix + 1; insn->len > 0; insn++)
{
if (!i386_match_pattern (current_pc, *insn))
return 0;
current_pc += insn->len;
}
return 1;
}
/* Some special instructions that might be migrated by GCC into the
part of the prologue that sets up the new stack frame. Because the
stack frame hasn't been setup yet, no registers have been saved
yet, and only the scratch registers %eax, %ecx and %edx can be
touched. */
static i386_insn i386_frame_setup_skip_insns[] =
{
/* Check for `movb imm8, r' and `movl imm32, r'.
??? Should we handle 16-bit operand-sizes here? */
/* `movb imm8, %al' and `movb imm8, %ah' */
/* `movb imm8, %cl' and `movb imm8, %ch' */
{ 2, { 0xb0, 0x00 }, { 0xfa, 0x00 } },
/* `movb imm8, %dl' and `movb imm8, %dh' */
{ 2, { 0xb2, 0x00 }, { 0xfb, 0x00 } },
/* `movl imm32, %eax' and `movl imm32, %ecx' */
{ 5, { 0xb8 }, { 0xfe } },
/* `movl imm32, %edx' */
{ 5, { 0xba }, { 0xff } },
/* Check for `mov imm32, r32'. Note that there is an alternative
encoding for `mov m32, %eax'.
??? Should we handle SIB addressing here?
??? Should we handle 16-bit operand-sizes here? */
/* `movl m32, %eax' */
{ 5, { 0xa1 }, { 0xff } },
/* `movl m32, %eax' and `mov; m32, %ecx' */
{ 6, { 0x89, 0x05 }, {0xff, 0xf7 } },
/* `movl m32, %edx' */
{ 6, { 0x89, 0x15 }, {0xff, 0xff } },
/* Check for `xorl r32, r32' and the equivalent `subl r32, r32'.
Because of the symmetry, there are actually two ways to encode
these instructions; opcode bytes 0x29 and 0x2b for `subl' and
opcode bytes 0x31 and 0x33 for `xorl'. */
/* `subl %eax, %eax' */
{ 2, { 0x29, 0xc0 }, { 0xfd, 0xff } },
/* `subl %ecx, %ecx' */
{ 2, { 0x29, 0xc9 }, { 0xfd, 0xff } },
/* `subl %edx, %edx' */
{ 2, { 0x29, 0xd2 }, { 0xfd, 0xff } },
/* `xorl %eax, %eax' */
{ 2, { 0x31, 0xc0 }, { 0xfd, 0xff } },
/* `xorl %ecx, %ecx' */
{ 2, { 0x31, 0xc9 }, { 0xfd, 0xff } },
/* `xorl %edx, %edx' */
{ 2, { 0x31, 0xd2 }, { 0xfd, 0xff } },
{ 0 }
};
/* Check whether PC points to an endbr32 instruction. */
static CORE_ADDR
i386_skip_endbr (CORE_ADDR pc)
{
static const gdb_byte endbr32[] = { 0xf3, 0x0f, 0x1e, 0xfb };
gdb_byte buf[sizeof (endbr32)];
/* Stop there if we can't read the code */
if (target_read_code (pc, buf, sizeof (endbr32)))
return pc;
/* If the instruction isn't an endbr32, stop */
if (memcmp (buf, endbr32, sizeof (endbr32)) != 0)
return pc;
return pc + sizeof (endbr32);
}
/* Check whether PC points to a no-op instruction. */
static CORE_ADDR
i386_skip_noop (CORE_ADDR pc)
{
gdb_byte op;
int check = 1;
if (target_read_code (pc, &op, 1))
return pc;
while (check)
{
check = 0;
/* Ignore `nop' instruction. */
if (op == 0x90)
{
pc += 1;
if (target_read_code (pc, &op, 1))
return pc;
check = 1;
}
/* Ignore no-op instruction `mov %edi, %edi'.
Microsoft system dlls often start with
a `mov %edi,%edi' instruction.
The 5 bytes before the function start are
filled with `nop' instructions.
This pattern can be used for hot-patching:
The `mov %edi, %edi' instruction can be replaced by a
near jump to the location of the 5 `nop' instructions
which can be replaced by a 32-bit jump to anywhere
in the 32-bit address space. */
else if (op == 0x8b)
{
if (target_read_code (pc + 1, &op, 1))
return pc;
if (op == 0xff)
{
pc += 2;
if (target_read_code (pc, &op, 1))
return pc;
check = 1;
}
}
}
return pc;
}
/* Check whether PC points at a code that sets up a new stack frame.
If so, it updates CACHE and returns the address of the first
instruction after the sequence that sets up the frame or LIMIT,
whichever is smaller. If we don't recognize the code, return PC. */
static CORE_ADDR
i386_analyze_frame_setup (struct gdbarch *gdbarch,
CORE_ADDR pc, CORE_ADDR limit,
struct i386_frame_cache *cache)
{
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
struct i386_insn *insn;
gdb_byte op;
int skip = 0;
if (limit <= pc)
return limit;
if (target_read_code (pc, &op, 1))
return pc;
if (op == 0x55) /* pushl %ebp */
{
/* Take into account that we've executed the `pushl %ebp' that
starts this instruction sequence. */
cache->saved_regs[I386_EBP_REGNUM] = 0;
cache->sp_offset += 4;
pc++;
/* If that's all, return now. */
if (limit <= pc)
return limit;
/* Check for some special instructions that might be migrated by
GCC into the prologue and skip them. At this point in the
prologue, code should only touch the scratch registers %eax,
%ecx and %edx, so while the number of possibilities is sheer,
it is limited.
Make sure we only skip these instructions if we later see the
`movl %esp, %ebp' that actually sets up the frame. */
while (pc + skip < limit)
{
insn = i386_match_insn (pc + skip, i386_frame_setup_skip_insns);
if (insn == NULL)
break;
skip += insn->len;
}
/* If that's all, return now. */
if (limit <= pc + skip)
return limit;
if (target_read_code (pc + skip, &op, 1))
return pc + skip;
/* The i386 prologue looks like
push %ebp
mov %esp,%ebp
sub $0x10,%esp
and a different prologue can be generated for atom.
push %ebp
lea (%esp),%ebp
lea -0x10(%esp),%esp
We handle both of them here. */
switch (op)
{
/* Check for `movl %esp, %ebp' -- can be written in two ways. */
case 0x8b:
if (read_code_unsigned_integer (pc + skip + 1, 1, byte_order)
!= 0xec)
return pc;
pc += (skip + 2);
break;
case 0x89:
if (read_code_unsigned_integer (pc + skip + 1, 1, byte_order)
!= 0xe5)
return pc;
pc += (skip + 2);
break;
case 0x8d: /* Check for 'lea (%ebp), %ebp'. */
if (read_code_unsigned_integer (pc + skip + 1, 2, byte_order)
!= 0x242c)
return pc;
pc += (skip + 3);
break;
default:
return pc;
}
/* OK, we actually have a frame. We just don't know how large
it is yet. Set its size to zero. We'll adjust it if
necessary. We also now commit to skipping the special
instructions mentioned before. */
cache->locals = 0;
/* If that's all, return now. */
if (limit <= pc)
return limit;
/* Check for stack adjustment
subl $XXX, %esp
or
lea -XXX(%esp),%esp
NOTE: You can't subtract a 16-bit immediate from a 32-bit
reg, so we don't have to worry about a data16 prefix. */
if (target_read_code (pc, &op, 1))
return pc;
if (op == 0x83)
{
/* `subl' with 8-bit immediate. */
if (read_code_unsigned_integer (pc + 1, 1, byte_order) != 0xec)
/* Some instruction starting with 0x83 other than `subl'. */
return pc;
/* `subl' with signed 8-bit immediate (though it wouldn't
make sense to be negative). */
cache->locals = read_code_integer (pc + 2, 1, byte_order);
return pc + 3;
}
else if (op == 0x81)
{
/* Maybe it is `subl' with a 32-bit immediate. */
if (read_code_unsigned_integer (pc + 1, 1, byte_order) != 0xec)
/* Some instruction starting with 0x81 other than `subl'. */
return pc;
/* It is `subl' with a 32-bit immediate. */
cache->locals = read_code_integer (pc + 2, 4, byte_order);
return pc + 6;
}
else if (op == 0x8d)
{
/* The ModR/M byte is 0x64. */
if (read_code_unsigned_integer (pc + 1, 1, byte_order) != 0x64)
return pc;
/* 'lea' with 8-bit displacement. */
cache->locals = -1 * read_code_integer (pc + 3, 1, byte_order);
return pc + 4;
}
else
{
/* Some instruction other than `subl' nor 'lea'. */
return pc;
}
}
else if (op == 0xc8) /* enter */
{
cache->locals = read_code_unsigned_integer (pc + 1, 2, byte_order);
return pc + 4;
}
return pc;
}
/* Check whether PC points at code that saves registers on the stack.
If so, it updates CACHE and returns the address of the first
instruction after the register saves or CURRENT_PC, whichever is
smaller. Otherwise, return PC. */
static CORE_ADDR
i386_analyze_register_saves (CORE_ADDR pc, CORE_ADDR current_pc,
struct i386_frame_cache *cache)
{
CORE_ADDR offset = 0;
gdb_byte op;
int i;
if (cache->locals > 0)
offset -= cache->locals;
for (i = 0; i < 8 && pc < current_pc; i++)
{
if (target_read_code (pc, &op, 1))
return pc;
if (op < 0x50 || op > 0x57)
break;
offset -= 4;
cache->saved_regs[op - 0x50] = offset;
cache->sp_offset += 4;
pc++;
}
return pc;
}
/* Do a full analysis of the prologue at PC and update CACHE
accordingly. Bail out early if CURRENT_PC is reached. Return the
address where the analysis stopped.
We handle these cases:
The startup sequence can be at the start of the function, or the
function can start with a branch to startup code at the end.
%ebp can be set up with either the 'enter' instruction, or "pushl
%ebp, movl %esp, %ebp" (`enter' is too slow to be useful, but was
once used in the System V compiler).
Local space is allocated just below the saved %ebp by either the
'enter' instruction, or by "subl $<size>, %esp". 'enter' has a
16-bit unsigned argument for space to allocate, and the 'addl'
instruction could have either a signed byte, or 32-bit immediate.
Next, the registers used by this function are pushed. With the
System V compiler they will always be in the order: %edi, %esi,
%ebx (and sometimes a harmless bug causes it to also save but not
restore %eax); however, the code below is willing to see the pushes
in any order, and will handle up to 8 of them.
If the setup sequence is at the end of the function, then the next
instruction will be a branch back to the start. */
static CORE_ADDR
i386_analyze_prologue (struct gdbarch *gdbarch,
CORE_ADDR pc, CORE_ADDR current_pc,
struct i386_frame_cache *cache)
{
pc = i386_skip_endbr (pc);
pc = i386_skip_noop (pc);
pc = i386_follow_jump (gdbarch, pc);
pc = i386_analyze_struct_return (pc, current_pc, cache);
pc = i386_skip_probe (pc);
pc = i386_analyze_stack_align (pc, current_pc, cache);
pc = i386_analyze_frame_setup (gdbarch, pc, current_pc, cache);
return i386_analyze_register_saves (pc, current_pc, cache);
}
/* Return PC of first real instruction. */
static CORE_ADDR
i386_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc)
{
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
static gdb_byte pic_pat[6] =
{
0xe8, 0, 0, 0, 0, /* call 0x0 */
0x5b, /* popl %ebx */
};
struct i386_frame_cache cache;
CORE_ADDR pc;
gdb_byte op;
int i;
CORE_ADDR func_addr;
if (find_pc_partial_function (start_pc, NULL, &func_addr, NULL))
{
CORE_ADDR post_prologue_pc
= skip_prologue_using_sal (gdbarch, func_addr);
struct compunit_symtab *cust = find_pc_compunit_symtab (func_addr);
/* LLVM backend (Clang/Flang) always emits a line note before the
prologue and another one after. We trust clang and newer Intel
compilers to emit usable line notes. */
if (post_prologue_pc
&& (cust != NULL
&& cust->producer () != NULL
&& (producer_is_llvm (cust->producer ())
|| producer_is_icc_ge_19 (cust->producer ()))))
return std::max (start_pc, post_prologue_pc);
}
cache.locals = -1;
pc = i386_analyze_prologue (gdbarch, start_pc, 0xffffffff, &cache);
if (cache.locals < 0)
return start_pc;
/* Found valid frame setup. */
/* The native cc on SVR4 in -K PIC mode inserts the following code
to get the address of the global offset table (GOT) into register
%ebx:
call 0x0
popl %ebx
movl %ebx,x(%ebp) (optional)
addl y,%ebx
This code is with the rest of the prologue (at the end of the
function), so we have to skip it to get to the first real
instruction at the start of the function. */
for (i = 0; i < 6; i++)
{
if (target_read_code (pc + i, &op, 1))
return pc;
if (pic_pat[i] != op)
break;
}
if (i == 6)
{
int delta = 6;
if (target_read_code (pc + delta, &op, 1))
return pc;
if (op == 0x89) /* movl %ebx, x(%ebp) */
{
op = read_code_unsigned_integer (pc + delta + 1, 1, byte_order);
if (op == 0x5d) /* One byte offset from %ebp. */
delta += 3;
else if (op == 0x9d) /* Four byte offset from %ebp. */
delta += 6;
else /* Unexpected instruction. */
delta = 0;
if (target_read_code (pc + delta, &op, 1))
return pc;
}
/* addl y,%ebx */
if (delta > 0 && op == 0x81
&& read_code_unsigned_integer (pc + delta + 1, 1, byte_order)
== 0xc3)
{
pc += delta + 6;
}
}
/* If the function starts with a branch (to startup code at the end)
the last instruction should bring us back to the first
instruction of the real code. */
if (i386_follow_jump (gdbarch, start_pc) != start_pc)
pc = i386_follow_jump (gdbarch, pc);
return pc;
}
/* Check that the code pointed to by PC corresponds to a call to
__main, skip it if so. Return PC otherwise. */
CORE_ADDR
i386_skip_main_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
{
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
gdb_byte op;
if (target_read_code (pc, &op, 1))
return pc;
if (op == 0xe8)
{
gdb_byte buf[4];
if (target_read_code (pc + 1, buf, sizeof buf) == 0)
{
/* Make sure address is computed correctly as a 32bit
integer even if CORE_ADDR is 64 bit wide. */
CORE_ADDR call_dest;
call_dest = pc + 5 + extract_signed_integer (buf, 4, byte_order);
call_dest = call_dest & 0xffffffffU;
bound_minimal_symbol s = lookup_minimal_symbol_by_pc (call_dest);
if (s.minsym != NULL
&& s.minsym->linkage_name () != NULL
&& strcmp (s.minsym->linkage_name (), "__main") == 0)
pc += 5;
}
}
return pc;
}
/* This function is 64-bit safe. */
static CORE_ADDR
i386_unwind_pc (struct gdbarch *gdbarch, const frame_info_ptr &next_frame)
{
gdb_byte buf[8];
frame_unwind_register (next_frame, gdbarch_pc_regnum (gdbarch), buf);
return extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr);
}
/* Normal frames. */
static void
i386_frame_cache_1 (const frame_info_ptr &this_frame,
struct i386_frame_cache *cache)
{
struct gdbarch *gdbarch = get_frame_arch (this_frame);
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
gdb_byte buf[4];
int i;
cache->pc = get_frame_func (this_frame);
/* In principle, for normal frames, %ebp holds the frame pointer,
which holds the base address for the current stack frame.
However, for functions that don't need it, the frame pointer is
optional. For these "frameless" functions the frame pointer is
actually the frame pointer of the calling frame. Signal
trampolines are just a special case of a "frameless" function.
They (usually) share their frame pointer with the frame that was
in progress when the signal occurred. */
get_frame_register (this_frame, I386_EBP_REGNUM, buf);
cache->base = extract_unsigned_integer (buf, 4, byte_order);
if (cache->base == 0)
{
cache->base_p = 1;
return;
}
/* For normal frames, %eip is stored at 4(%ebp). */
cache->saved_regs[I386_EIP_REGNUM] = 4;
if (cache->pc != 0)
i386_analyze_prologue (gdbarch, cache->pc, get_frame_pc (this_frame),
cache);
if (cache->locals < 0)
{
/* We didn't find a valid frame, which means that CACHE->base
currently holds the frame pointer for our calling frame. If
we're at the start of a function, or somewhere half-way its
prologue, the function's frame probably hasn't been fully
setup yet. Try to reconstruct the base address for the stack
frame by looking at the stack pointer. For truly "frameless"
functions this might work too. */
if (cache->saved_sp_reg != -1)
{
/* Saved stack pointer has been saved. */
get_frame_register (this_frame, cache->saved_sp_reg, buf);
cache->saved_sp = extract_unsigned_integer (buf, 4, byte_order);
/* We're halfway aligning the stack. */
cache->base = ((cache->saved_sp - 4) & 0xfffffff0) - 4;
cache->saved_regs[I386_EIP_REGNUM] = cache->saved_sp - 4;
/* This will be added back below. */
cache->saved_regs[I386_EIP_REGNUM] -= cache->base;
}
else if (cache->pc != 0
|| target_read_code (get_frame_pc (this_frame), buf, 1))
{
/* We're in a known function, but did not find a frame
setup. Assume that the function does not use %ebp.
Alternatively, we may have jumped to an invalid
address; in that case there is definitely no new
frame in %ebp. */
get_frame_register (this_frame, I386_ESP_REGNUM, buf);
cache->base = extract_unsigned_integer (buf, 4, byte_order)
+ cache->sp_offset;
}
else
/* We're in an unknown function. We could not find the start
of the function to analyze the prologue; our best option is
to assume a typical frame layout with the caller's %ebp
saved. */
cache->saved_regs[I386_EBP_REGNUM] = 0;
}
if (cache->saved_sp_reg != -1)
{
/* Saved stack pointer has been saved (but the SAVED_SP_REG
register may be unavailable). */
if (cache->saved_sp == 0
&& deprecated_frame_register_read (this_frame,
cache->saved_sp_reg, buf))
cache->saved_sp = extract_unsigned_integer (buf, 4, byte_order);
}
/* Now that we have the base address for the stack frame we can
calculate the value of %esp in the calling frame. */
else if (cache->saved_sp == 0)
cache->saved_sp = cache->base + 8;
/* Adjust all the saved registers such that they contain addresses
instead of offsets. */
for (i = 0; i < I386_NUM_SAVED_REGS; i++)
if (cache->saved_regs[i] != -1)
cache->saved_regs[i] += cache->base;
cache->base_p = 1;
}
static struct i386_frame_cache *
i386_frame_cache (const frame_info_ptr &this_frame, void **this_cache)
{
struct i386_frame_cache *cache;
if (*this_cache)
return (struct i386_frame_cache *) *this_cache;
cache = i386_alloc_frame_cache ();
*this_cache = cache;
try
{
i386_frame_cache_1 (this_frame, cache);
}
catch (const gdb_exception_error &ex)
{
if (ex.error != NOT_AVAILABLE_ERROR)
throw;
}
return cache;
}
static void
i386_frame_this_id (const frame_info_ptr &this_frame, void **this_cache,
struct frame_id *this_id)
{
struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache);
if (!cache->base_p)
(*this_id) = frame_id_build_unavailable_stack (cache->pc);
else if (cache->base == 0)
{
/* This marks the outermost frame. */
}
else
{
/* See the end of i386_push_dummy_call. */
(*this_id) = frame_id_build (cache->base + 8, cache->pc);
}
}
static enum unwind_stop_reason
i386_frame_unwind_stop_reason (const frame_info_ptr &this_frame,
void **this_cache)
{
struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache);
if (!cache->base_p)
return UNWIND_UNAVAILABLE;
/* This marks the outermost frame. */
if (cache->base == 0)
return UNWIND_OUTERMOST;
return UNWIND_NO_REASON;
}
static struct value *
i386_frame_prev_register (const frame_info_ptr &this_frame, void **this_cache,
int regnum)
{
struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache);
gdb_assert (regnum >= 0);
/* The System V ABI says that:
"The flags register contains the system flags, such as the
direction flag and the carry flag. The direction flag must be
set to the forward (that is, zero) direction before entry and
upon exit from a function. Other user flags have no specified
role in the standard calling sequence and are not preserved."
To guarantee the "upon exit" part of that statement we fake a
saved flags register that has its direction flag cleared.
Note that GCC doesn't seem to rely on the fact that the direction
flag is cleared after a function return; it always explicitly
clears the flag before operations where it matters.
FIXME: kettenis/20030316: I'm not quite sure whether this is the
right thing to do. The way we fake the flags register here makes
it impossible to change it. */
if (regnum == I386_EFLAGS_REGNUM)
{
ULONGEST val;
val = get_frame_register_unsigned (this_frame, regnum);
val &= ~(1 << 10);
return frame_unwind_got_constant (this_frame, regnum, val);
}
if (regnum == I386_EIP_REGNUM && cache->pc_in_eax)
return frame_unwind_got_register (this_frame, regnum, I386_EAX_REGNUM);
if (regnum == I386_ESP_REGNUM
&& (cache->saved_sp != 0 || cache->saved_sp_reg != -1))
{
/* If the SP has been saved, but we don't know where, then this
means that SAVED_SP_REG register was found unavailable back
when we built the cache. */
if (cache->saved_sp == 0)
return frame_unwind_got_register (this_frame, regnum,
cache->saved_sp_reg);
else
return frame_unwind_got_constant (this_frame, regnum,
cache->saved_sp);
}
if (regnum < I386_NUM_SAVED_REGS && cache->saved_regs[regnum] != -1)
return frame_unwind_got_memory (this_frame, regnum,
cache->saved_regs[regnum]);
return frame_unwind_got_register (this_frame, regnum, regnum);
}
static const struct frame_unwind i386_frame_unwind =
{
"i386 prologue",
NORMAL_FRAME,
i386_frame_unwind_stop_reason,
i386_frame_this_id,
i386_frame_prev_register,
NULL,
default_frame_sniffer
};
/* Normal frames, but in a function epilogue. */
/* Implement the stack_frame_destroyed_p gdbarch method.
The epilogue is defined here as the 'ret' instruction, which will
follow any instruction such as 'leave' or 'pop %ebp' that destroys
the function's stack frame. */
static int
i386_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc)
{
gdb_byte insn;
if (target_read_memory (pc, &insn, 1))
return 0; /* Can't read memory at pc. */
if (insn != 0xc3) /* 'ret' instruction. */
return 0;
return 1;
}
static int
i386_epilogue_frame_sniffer_1 (const struct frame_unwind *self,
const frame_info_ptr &this_frame,
void **this_prologue_cache, bool override_p)
{
struct gdbarch *gdbarch = get_frame_arch (this_frame);
CORE_ADDR pc = get_frame_pc (this_frame);
if (frame_relative_level (this_frame) != 0)
/* We're not in the inner frame, so assume we're not in an epilogue. */
return 0;
bool unwind_valid_p
= compunit_epilogue_unwind_valid (find_pc_compunit_symtab (pc));
if (override_p)
{
if (unwind_valid_p)
/* Don't override the symtab unwinders, skip
"i386 epilogue override". */
return 0;
}
else
{
if (!unwind_valid_p)
/* "i386 epilogue override" unwinder already ran, skip
"i386 epilogue". */
return 0;
}
/* Check whether we're in an epilogue. */
return i386_stack_frame_destroyed_p (gdbarch, pc);
}
static int
i386_epilogue_override_frame_sniffer (const struct frame_unwind *self,
const frame_info_ptr &this_frame,
void **this_prologue_cache)
{
return i386_epilogue_frame_sniffer_1 (self, this_frame, this_prologue_cache,
true);
}
static int
i386_epilogue_frame_sniffer (const struct frame_unwind *self,
const frame_info_ptr &this_frame,
void **this_prologue_cache)
{
return i386_epilogue_frame_sniffer_1 (self, this_frame, this_prologue_cache,
false);
}
static struct i386_frame_cache *
i386_epilogue_frame_cache (const frame_info_ptr &this_frame, void **this_cache)
{
struct i386_frame_cache *cache;
CORE_ADDR sp;
if (*this_cache)
return (struct i386_frame_cache *) *this_cache;
cache = i386_alloc_frame_cache ();
*this_cache = cache;
try
{
cache->pc = get_frame_func (this_frame);
/* At this point the stack looks as if we just entered the
function, with the return address at the top of the
stack. */
sp = get_frame_register_unsigned (this_frame, I386_ESP_REGNUM);
cache->base = sp + cache->sp_offset;
cache->saved_sp = cache->base + 8;
cache->saved_regs[I386_EIP_REGNUM] = cache->base + 4;
cache->base_p = 1;
}
catch (const gdb_exception_error &ex)
{
if (ex.error != NOT_AVAILABLE_ERROR)
throw;
}
return cache;
}
static enum unwind_stop_reason
i386_epilogue_frame_unwind_stop_reason (const frame_info_ptr &this_frame,
void **this_cache)
{
struct i386_frame_cache *cache =
i386_epilogue_frame_cache (this_frame, this_cache);
if (!cache->base_p)
return UNWIND_UNAVAILABLE;
return UNWIND_NO_REASON;
}
static void
i386_epilogue_frame_this_id (const frame_info_ptr &this_frame,
void **this_cache,
struct frame_id *this_id)
{
struct i386_frame_cache *cache =
i386_epilogue_frame_cache (this_frame, this_cache);
if (!cache->base_p)
(*this_id) = frame_id_build_unavailable_stack (cache->pc);
else
(*this_id) = frame_id_build (cache->base + 8, cache->pc);
}
static struct value *
i386_epilogue_frame_prev_register (const frame_info_ptr &this_frame,
void **this_cache, int regnum)
{
/* Make sure we've initialized the cache. */
i386_epilogue_frame_cache (this_frame, this_cache);
return i386_frame_prev_register (this_frame, this_cache, regnum);
}
static const struct frame_unwind i386_epilogue_override_frame_unwind =
{
"i386 epilogue override",
NORMAL_FRAME,
i386_epilogue_frame_unwind_stop_reason,
i386_epilogue_frame_this_id,
i386_epilogue_frame_prev_register,
NULL,
i386_epilogue_override_frame_sniffer
};
static const struct frame_unwind i386_epilogue_frame_unwind =
{
"i386 epilogue",
NORMAL_FRAME,
i386_epilogue_frame_unwind_stop_reason,
i386_epilogue_frame_this_id,
i386_epilogue_frame_prev_register,
NULL,
i386_epilogue_frame_sniffer
};
/* Stack-based trampolines. */
/* These trampolines are used on cross x86 targets, when taking the
address of a nested function. When executing these trampolines,
no stack frame is set up, so we are in a similar situation as in
epilogues and i386_epilogue_frame_this_id can be re-used. */
/* Static chain passed in register. */
static i386_insn i386_tramp_chain_in_reg_insns[] =
{
/* `movl imm32, %eax' and `movl imm32, %ecx' */
{ 5, { 0xb8 }, { 0xfe } },
/* `jmp imm32' */
{ 5, { 0xe9 }, { 0xff } },
{0}
};
/* Static chain passed on stack (when regparm=3). */
static i386_insn i386_tramp_chain_on_stack_insns[] =
{
/* `push imm32' */
{ 5, { 0x68 }, { 0xff } },
/* `jmp imm32' */
{ 5, { 0xe9 }, { 0xff } },
{0}
};
/* Return whether PC points inside a stack trampoline. */
static int
i386_in_stack_tramp_p (CORE_ADDR pc)
{
gdb_byte insn;
const char *name;
/* A stack trampoline is detected if no name is associated
to the current pc and if it points inside a trampoline
sequence. */
find_pc_partial_function (pc, &name, NULL, NULL);
if (name)
return 0;
if (target_read_memory (pc, &insn, 1))
return 0;
if (!i386_match_insn_block (pc, i386_tramp_chain_in_reg_insns)
&& !i386_match_insn_block (pc, i386_tramp_chain_on_stack_insns))
return 0;
return 1;
}
static int
i386_stack_tramp_frame_sniffer (const struct frame_unwind *self,
const frame_info_ptr &this_frame,
void **this_cache)
{
if (frame_relative_level (this_frame) == 0)
return i386_in_stack_tramp_p (get_frame_pc (this_frame));
else
return 0;
}
static const struct frame_unwind i386_stack_tramp_frame_unwind =
{
"i386 stack tramp",
NORMAL_FRAME,
i386_epilogue_frame_unwind_stop_reason,
i386_epilogue_frame_this_id,
i386_epilogue_frame_prev_register,
NULL,
i386_stack_tramp_frame_sniffer
};
/* Generate a bytecode expression to get the value of the saved PC. */
static void
i386_gen_return_address (struct gdbarch *gdbarch,
struct agent_expr *ax, struct axs_value *value,
CORE_ADDR scope)
{
/* The following sequence assumes the traditional use of the base
register. */
ax_reg (ax, I386_EBP_REGNUM);
ax_const_l (ax, 4);
ax_simple (ax, aop_add);
value->type = register_type (gdbarch, I386_EIP_REGNUM);
value->kind = axs_lvalue_memory;
}
/* Signal trampolines. */
static struct i386_frame_cache *
i386_sigtramp_frame_cache (const frame_info_ptr &this_frame, void **this_cache)
{
struct gdbarch *gdbarch = get_frame_arch (this_frame);
i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch);
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
struct i386_frame_cache *cache;
CORE_ADDR addr;
gdb_byte buf[4];
if (*this_cache)
return (struct i386_frame_cache *) *this_cache;
cache = i386_alloc_frame_cache ();
try
{
get_frame_register (this_frame, I386_ESP_REGNUM, buf);
cache->base = extract_unsigned_integer (buf, 4, byte_order) - 4;
addr = tdep->sigcontext_addr (this_frame);
if (tdep->sc_reg_offset)
{
int i;
gdb_assert (tdep->sc_num_regs <= I386_NUM_SAVED_REGS);
for (i = 0; i < tdep->sc_num_regs; i++)
if (tdep->sc_reg_offset[i] != -1)
cache->saved_regs[i] = addr + tdep->sc_reg_offset[i];
}
else
{
cache->saved_regs[I386_EIP_REGNUM] = addr + tdep->sc_pc_offset;
cache->saved_regs[I386_ESP_REGNUM] = addr + tdep->sc_sp_offset;
}
cache->base_p = 1;
}
catch (const gdb_exception_error &ex)
{
if (ex.error != NOT_AVAILABLE_ERROR)
throw;
}
*this_cache = cache;
return cache;
}
static enum unwind_stop_reason
i386_sigtramp_frame_unwind_stop_reason (const frame_info_ptr &this_frame,
void **this_cache)
{
struct i386_frame_cache *cache =
i386_sigtramp_frame_cache (this_frame, this_cache);
if (!cache->base_p)
return UNWIND_UNAVAILABLE;
return UNWIND_NO_REASON;
}
static void
i386_sigtramp_frame_this_id (const frame_info_ptr &this_frame, void **this_cache,
struct frame_id *this_id)
{
struct i386_frame_cache *cache =
i386_sigtramp_frame_cache (this_frame, this_cache);
if (!cache->base_p)
(*this_id) = frame_id_build_unavailable_stack (get_frame_pc (this_frame));
else
{
/* See the end of i386_push_dummy_call. */
(*this_id) = frame_id_build (cache->base + 8, get_frame_pc (this_frame));
}
}
static struct value *
i386_sigtramp_frame_prev_register (const frame_info_ptr &this_frame,
void **this_cache, int regnum)
{
/* Make sure we've initialized the cache. */
i386_sigtramp_frame_cache (this_frame, this_cache);
return i386_frame_prev_register (this_frame, this_cache, regnum);
}
static int
i386_sigtramp_frame_sniffer (const struct frame_unwind *self,
const frame_info_ptr &this_frame,
void **this_prologue_cache)
{
gdbarch *arch = get_frame_arch (this_frame);
i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (arch);
/* We shouldn't even bother if we don't have a sigcontext_addr
handler. */
if (tdep->sigcontext_addr == NULL)
return 0;
if (tdep->sigtramp_p != NULL)
{
if (tdep->sigtramp_p (this_frame))
return 1;
}
if (tdep->sigtramp_start != 0)
{
CORE_ADDR pc = get_frame_pc (this_frame);
gdb_assert (tdep->sigtramp_end != 0);
if (pc >= tdep->sigtramp_start && pc < tdep->sigtramp_end)
return 1;
}
return 0;
}
static const struct frame_unwind i386_sigtramp_frame_unwind =
{
"i386 sigtramp",
SIGTRAMP_FRAME,
i386_sigtramp_frame_unwind_stop_reason,
i386_sigtramp_frame_this_id,
i386_sigtramp_frame_prev_register,
NULL,
i386_sigtramp_frame_sniffer
};
static CORE_ADDR
i386_frame_base_address (const frame_info_ptr &this_frame, void **this_cache)
{
struct i386_frame_cache *cache = i386_frame_cache (this_frame, this_cache);
return cache->base;
}
static const struct frame_base i386_frame_base =
{
&i386_frame_unwind,
i386_frame_base_address,
i386_frame_base_address,
i386_frame_base_address
};
static struct frame_id
i386_dummy_id (struct gdbarch *gdbarch, const frame_info_ptr &this_frame)
{
CORE_ADDR fp;
fp = get_frame_register_unsigned (this_frame, I386_EBP_REGNUM);
/* See the end of i386_push_dummy_call. */
return frame_id_build (fp + 8, get_frame_pc (this_frame));
}
/* _Decimal128 function return values need 16-byte alignment on the
stack. */
static CORE_ADDR
i386_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
{
return sp & -(CORE_ADDR)16;
}
/* Figure out where the longjmp will land. Slurp the args out of the
stack. We expect the first arg to be a pointer to the jmp_buf
structure from which we extract the address that we will land at.
This address is copied into PC. This routine returns non-zero on
success. */
static int
i386_get_longjmp_target (const frame_info_ptr &frame, CORE_ADDR *pc)
{
gdb_byte buf[4];
CORE_ADDR sp, jb_addr;
struct gdbarch *gdbarch = get_frame_arch (frame);
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch);
int jb_pc_offset = tdep->jb_pc_offset;
/* If JB_PC_OFFSET is -1, we have no way to find out where the
longjmp will land. */
if (jb_pc_offset == -1)
return 0;
get_frame_register (frame, I386_ESP_REGNUM, buf);
sp = extract_unsigned_integer (buf, 4, byte_order);
if (target_read_memory (sp + 4, buf, 4))
return 0;
jb_addr = extract_unsigned_integer (buf, 4, byte_order);
if (target_read_memory (jb_addr + jb_pc_offset, buf, 4))
return 0;
*pc = extract_unsigned_integer (buf, 4, byte_order);
return 1;
}
/* Check whether TYPE must be 16-byte-aligned when passed as a
function argument. 16-byte vectors, _Decimal128 and structures or
unions containing such types must be 16-byte-aligned; other
arguments are 4-byte-aligned. */
static int
i386_16_byte_align_p (struct type *type)
{
type = check_typedef (type);
if ((type->code () == TYPE_CODE_DECFLOAT
|| (type->code () == TYPE_CODE_ARRAY && type->is_vector ()))
&& type->length () == 16)
return 1;
if (type->code () == TYPE_CODE_ARRAY)
return i386_16_byte_align_p (type->target_type ());
if (type->code () == TYPE_CODE_STRUCT
|| type->code () == TYPE_CODE_UNION)
{
int i;
for (i = 0; i < type->num_fields (); i++)
{
if (type->field (i).is_static ())
continue;
if (i386_16_byte_align_p (type->field (i).type ()))
return 1;
}
}
return 0;
}
/* Implementation for set_gdbarch_push_dummy_code. */
static CORE_ADDR
i386_push_dummy_code (struct gdbarch *gdbarch, CORE_ADDR sp, CORE_ADDR funaddr,
struct value **args, int nargs, struct type *value_type,
CORE_ADDR *real_pc, CORE_ADDR *bp_addr,
struct regcache *regcache)
{
/* Use 0xcc breakpoint - 1 byte. */
*bp_addr = sp - 1;
*real_pc = funaddr;
/* Keep the stack aligned. */
return sp - 16;
}
/* The "push_dummy_call" gdbarch method, optionally with the thiscall
calling convention. */
CORE_ADDR
i386_thiscall_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
struct regcache *regcache, CORE_ADDR bp_addr,
int nargs, struct value **args, CORE_ADDR sp,
function_call_return_method return_method,
CORE_ADDR struct_addr, bool thiscall)
{
enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
gdb_byte buf[4];
int i;
int write_pass;
int args_space = 0;
/* BND registers can be in arbitrary values at the moment of the
inferior call. This can cause boundary violations that are not
due to a real bug or even desired by the user. The best to be done
is set the BND registers to allow access to the whole memory, INIT
state, before pushing the inferior call. */
i387_reset_bnd_regs (gdbarch, regcache);
/* Determine the total space required for arguments and struct
return address in a first pass (allowing for 16-byte-aligned
arguments), then push arguments in a second pass. */
for (write_pass = 0; write_pass < 2; write_pass++)
{
int args_space_used = 0;
if (return_method == return_method_struct)
{
if (write_pass)
{
/* Push value address. */
store_unsigned_integer (buf, 4, byte_order, struct_addr);
write_memory (sp, buf, 4);
args_space_used += 4;
}
else
args_space += 4;
}
for (i = thiscall ? 1 : 0; i < nargs; i++)
{
int len = args[i]->enclosing_type ()->length ();
if (write_pass)
{
if (i386_16_byte_align_p (args[i]->enclosing_type ()))
args_space_used = align_up (args_space_used, 16);
write_memory (sp + args_space_used,
args[i]->contents_all ().data (), len);
/* The System V ABI says that:
"An argument's size is increased, if necessary, to make it a
multiple of [32-bit] words. This may require tail padding,
depending on the size of the argument."
This makes sure the stack stays word-aligned. */
args_space_used += align_up (len, 4);
}
else
{
if (i386_16_byte_align_p (args[i]->enclosing_type ()))
args_space = align_up (args_space, 16);
args_space += align_up (len, 4);
}
}
if (!write_pass)
{
sp -= args_space;
/* The original System V ABI only requires word alignment,
but modern incarnations need 16-byte alignment in order
to support SSE. Since wasting a few bytes here isn't
harmful we unconditionally enforce 16-byte alignment. */
sp &= ~0xf;
}
}
/* Store return address. */
sp -= 4;
store_unsigned_integer (buf, 4, byte_order, bp_addr);
write_memory (sp, buf, 4);
/* Finally, update the stack pointer... */
store_unsigned_integer (buf, 4, byte_order, sp);
regcache->cooked_write (I386_ESP_REGNUM, buf);
/* ...and fake a frame pointer. */
regcache->cooked_write (I386_EBP_REGNUM, buf);
/* The 'this' pointer needs to be in ECX. */
if (thiscall)
regcache->cooked_write (I386_ECX_REGNUM,
args[0]->contents_all ().data ());
/* If the PLT is position-independent, the SYSTEM V ABI requires %ebx to be
set to the address of the GOT when doing a call to a PLT address.
Note that we do not try to determine whether the PLT is
position-independent, we just set the register regardless. */
CORE_ADDR func_addr = find_function_addr (function, nullptr, nullptr);
if (in_plt_section (func_addr))
{
struct objfile *objf = nullptr;
asection *asect = nullptr;
obj_section *osect = nullptr;
/* Get object file containing func_addr. */
obj_section *func_section = find_pc_section (func_addr);
if (func_section != nullptr)
objf = func_section->objfile;
if (objf != nullptr)
{
/* Get corresponding .got.plt or .got section. */
asect = bfd_get_section_by_name (objf->obfd.get (), ".got.plt");
if (asect == nullptr)
asect = bfd_get_section_by_name (objf->obfd.get (), ".got");
}
if (asect != nullptr)
/* Translate asection to obj_section. */
osect = maint_obj_section_from_bfd_section (objf->obfd.get (),
asect, objf);
if (osect != nullptr)
{
/* Store the section address in %ebx. */
store_unsigned_integer (buf, 4, byte_order, osect->addr ());
regcache->cooked_write (I386_EBX_REGNUM, buf);
}
else
{
/* If we would only do this for a position-independent PLT, it would
make sense to issue a warning here. */
}
}
/* MarkK wrote: This "+ 8" is all over the place:
(i386_frame_this_id, i386_sigtramp_frame_this_id,
i386_dummy_id). It's there, since all frame unwinders for
a given target have to agree (within a certain margin) on the
definition of the stack address of a frame. Otherwise frame id
comparison might not work correctly. Since DWARF2/GCC uses the
stack address *before* the function call as a frame's CFA. On
the i386, when %ebp is used as a frame pointer, the offset
between the contents %ebp and the CFA as defined by GCC. */
return sp + 8;
}
/* Implement the "push_dummy_call" gdbarch method. */
static CORE_ADDR
i386_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
struct regcache *regcache, CORE_ADDR bp_addr, int nargs,
struct value **args, CORE_ADDR sp,
function_call_return_method return_method,
CORE_ADDR struct_addr)
{
return i386_thiscall_push_dummy_call (gdbarch, function, regcache, bp_addr,
nargs, args, sp, return_method,
struct_addr, false);
}
/* These registers are used for returning integers (and on some
targets also for returning `struct' and `union' values when their
size and alignment match an integer type). */
#define LOW_RETURN_REGNUM I386_EAX_REGNUM /* %eax */
#define HIGH_RETURN_REGNUM I386_EDX_REGNUM /* %edx */
/* Read, for architecture GDBARCH, a function return value of TYPE
from REGCACHE, and copy that into VALBUF. */
static void
i386_extract_return_value (struct gdbarch *gdbarch, struct type *type,
struct regcache *regcache, gdb_byte *valbuf)
{
i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch);
int len = type->length ();
gdb_byte buf[I386_MAX_REGISTER_SIZE];
/* _Float16 and _Float16 _Complex values are returned via xmm0. */
if (((type->code () == TYPE_CODE_FLT) && len == 2)
|| ((type->code () == TYPE_CODE_COMPLEX) && len == 4))
{
regcache->raw_read (I387_XMM0_REGNUM (tdep), valbuf);
return;
}
else if (type->code () == TYPE_CODE_FLT)
{
if (tdep->st0_regnum < 0)
{
warning (_("Cannot find floating-point return value."));
memset (valbuf, 0, len);
return;
}
/* Floating-point return values can be found in %st(0). Convert
its contents to the desired type. This is probably not
exactly how it would happen on the target itself, but it is
the best we can do. */
regcache->raw_read (I386_ST0_REGNUM, buf);
target_float_convert (buf, i387_ext_type (gdbarch), valbuf, type);
}
else
{
int low_size = register_size (gdbarch, LOW_RETURN_REGNUM);
int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM);
if (len <= low_size)
{
regcache->raw_read (LOW_RETURN_REGNUM, buf);
memcpy (valbuf, buf, len);
}
else if (len <= (low_size + high_size))
{
regcache->raw_read (LOW_RETURN_REGNUM, buf);
memcpy (valbuf, buf, low_size);
regcache->raw_read (HIGH_RETURN_REGNUM, buf);
memcpy (valbuf + low_size, buf, len - low_size);
}
else
internal_error (_("Cannot extract return value of %d bytes long."),
len);
}
}
/* Write, for architecture GDBARCH, a function return value of TYPE
from VALBUF into REGCACHE. */
static void
i386_store_return_value (struct gdbarch *gdbarch, struct type *type,
struct regcache *regcache, const gdb_byte *valbuf)
{
i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch);
int len = type->length ();
if (type->code () == TYPE_CODE_FLT)
{
ULONGEST fstat;
gdb_byte buf[I386_MAX_REGISTER_SIZE];
if (tdep->st0_regnum < 0)
{
warning (_("Cannot set floating-point return value."));
return;
}
/* Returning floating-point values is a bit tricky. Apart from
storing the return value in %st(0), we have to simulate the
state of the FPU at function return point. */
/* Convert the value found in VALBUF to the extended
floating-point format used by the FPU. This is probably
not exactly how it would happen on the target itself, but
it is the best we can do. */
target_float_convert (valbuf, type, buf, i387_ext_type (gdbarch));
regcache->raw_write (I386_ST0_REGNUM, buf);
/* Set the top of the floating-point register stack to 7. The
actual value doesn't really matter, but 7 is what a normal
function return would end up with if the program started out
with a freshly initialized FPU. */
regcache_raw_read_unsigned (regcache, I387_FSTAT_REGNUM (tdep), &fstat);
fstat |= (7 << 11);
regcache_raw_write_unsigned (regcache, I387_FSTAT_REGNUM (tdep), fstat);
/* Mark %st(1) through %st(7) as empty. Since we set the top of
the floating-point register stack to 7, the appropriate value
for the tag word is 0x3fff. */
regcache_raw_write_unsigned (regcache, I387_FTAG_REGNUM (tdep), 0x3fff);
}
else
{
int low_size = register_size (gdbarch, LOW_RETURN_REGNUM);
int high_size = register_size (gdbarch, HIGH_RETURN_REGNUM);
if (len <= low_size)
regcache->raw_write_part (LOW_RETURN_REGNUM, 0, len, valbuf);
else if (len <= (low_size + high_size))
{
regcache->raw_write (LOW_RETURN_REGNUM, valbuf);
regcache->raw_write_part (HIGH_RETURN_REGNUM, 0, len - low_size,
valbuf + low_size);
}
else
internal_error (_("Cannot store return value of %d bytes long."), len);
}
}
/* This is the variable that is set with "set struct-convention", and
its legitimate values. */
static const char default_struct_convention[] = "default";
static const char pcc_struct_convention[] = "pcc";
static const char reg_struct_convention[] = "reg";
static const char *const valid_conventions[] =
{
default_struct_convention,
pcc_struct_convention,
reg_struct_convention,
NULL
};
static const char *struct_convention = default_struct_convention;
/* Return non-zero if TYPE, which is assumed to be a structure,
a union type, or an array type, should be returned in registers
for architecture GDBARCH. */
static int
i386_reg_struct_return_p (struct gdbarch *gdbarch, struct type *type)
{
i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch);
enum type_code code = type->code ();
int len = type->length ();
gdb_assert (code == TYPE_CODE_STRUCT
|| code == TYPE_CODE_UNION
|| code == TYPE_CODE_ARRAY);
if (struct_convention == pcc_struct_convention
|| (struct_convention == default_struct_convention
&& tdep->struct_return == pcc_struct_return)
|| TYPE_HAS_DYNAMIC_LENGTH (type))
return 0;
/* Structures consisting of a single `float', `double' or 'long
double' member are returned in %st(0). */
if (code == TYPE_CODE_STRUCT && type->num_fields () == 1)
{
type = check_typedef (type->field (0).type ());
if (type->code () == TYPE_CODE_FLT)
return (len == 4 || len == 8 || len == 12);
}
return (len == 1 || len == 2 || len == 4 || len == 8);
}
/* Determine, for architecture GDBARCH, how a return value of TYPE
should be returned. If it is supposed to be returned in registers,
and READBUF is non-zero, read the appropriate value from REGCACHE,
and copy it into READBUF. If WRITEBUF is non-zero, write the value
from WRITEBUF into REGCACHE. */
static enum return_value_convention
i386_return_value (struct gdbarch *gdbarch, struct value *function,
struct type *type, struct regcache *regcache,
struct value **read_value, const gdb_byte *writebuf)
{
enum type_code code = type->code ();
if (((code == TYPE_CODE_STRUCT
|| code == TYPE_CODE_UNION
|| code == TYPE_CODE_ARRAY)
&& !i386_reg_struct_return_p (gdbarch, type))
/* Complex double and long double uses the struct return convention. */
|| (code == TYPE_CODE_COMPLEX && type->length () == 16)
|| (code == TYPE_CODE_COMPLEX && type->length () == 24)
/* 128-bit decimal float uses the struct return convention. */
|| (code == TYPE_CODE_DECFLOAT && type->length () == 16))
{
/* The System V ABI says that:
"A function that returns a structure or union also sets %eax
to the value of the original address of the caller's area
before it returns. Thus when the caller receives control
again, the address of the returned object resides in register
%eax and can be used to access the object."
So the ABI guarantees that we can always find the return
value just after the function has returned. */
/* Note that the ABI doesn't mention functions returning arrays,
which is something possible in certain languages such as Ada.
In this case, the value is returned as if it was wrapped in
a record, so the convention applied to records also applies
to arrays. */
if (read_value != nullptr)
{
ULONGEST addr;
regcache_raw_read_unsigned (regcache, I386_EAX_REGNUM, &addr);
*read_value = value_at_non_lval (type, addr);
}
return RETURN_VALUE_ABI_RETURNS_ADDRESS;
}
/* This special case is for structures consisting of a single
`float', `double' or 'long double' member. These structures are
returned in %st(0). For these structures, we call ourselves
recursively, changing TYPE into the type of the first member of
the structure. Since that should work for all structures that
have only one member, we don't bother to check the member's type
here. */
if (code == TYPE_CODE_STRUCT && type->num_fields () == 1)
{
struct type *inner_type = check_typedef (type->field (0).type ());
enum return_value_convention result
= i386_return_value (gdbarch, function, inner_type, regcache,
read_value, writebuf);
if (read_value != nullptr)
(*read_value)->deprecated_set_type (type);
return result;
}
if (read_value != nullptr)
{
*read_value = value::allocate (type);
i386_extract_return_value (gdbarch, type, regcache,
(*read_value)->contents_raw ().data ());
}
if (writebuf)
i386_store_return_value (gdbarch, type, regcache, writebuf);
return RETURN_VALUE_REGISTER_CONVENTION;
}
struct type *
i387_ext_type (struct gdbarch *gdbarch)
{
i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch);
if (!tdep->i387_ext_type)
{
tdep->i387_ext_type = tdesc_find_type (gdbarch, "i387_ext");
gdb_assert (tdep->i387_ext_type != NULL);
}
return tdep->i387_ext_type;
}
/* Construct type for pseudo BND registers. We can't use
tdesc_find_type since a complement of one value has to be used
to describe the upper bound. */
static struct type *
i386_bnd_type (struct gdbarch *gdbarch)
{
i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch);
if (!tdep->i386_bnd_type)
{
struct type *t;
const struct builtin_type *bt = builtin_type (gdbarch);
/* The type we're building is described bellow: */
#if 0
struct __bound128
{
void *lbound;
void *ubound; /* One complement of raw ubound field. */
};
#endif
t = arch_composite_type (gdbarch,
"__gdb_builtin_type_bound128", TYPE_CODE_STRUCT);
append_composite_type_field (t, "lbound", bt->builtin_data_ptr);
append_composite_type_field (t, "ubound", bt->builtin_data_ptr);
t->set_name ("builtin_type_bound128");
tdep->i386_bnd_type = t;
}
return tdep->i386_bnd_type;
}
/* Construct vector type for pseudo ZMM registers. We can't use
tdesc_find_type since ZMM isn't described in target description. */
static struct type *
i386_zmm_type (struct gdbarch *gdbarch)
{
i386_gdbarch_tdep *tdep = gdbarch_tdep<i386_gdbarch_tdep> (gdbarch);
if (!tdep->i386_zmm_type)
{
const struct builtin_type *bt = builtin_type (gdbarch);
/* The type we're building is this: */
#if 0
union __gdb_builtin_type_vec512i
{
int128_t v4_int128[4];
int64_t v8_int64[8];
int32_t v16_int32[16];
int16_t v32_int16[32];
int8_t v64_int8[64];
double v8_double[8];
float v16_float[16];
float16_t v32_half[32];
bfloat16_t v32_bfloat16[32];
};