| 2021-06-22 Mike Frysinger <vapier@gentoo.org> |
| |
| * configure.ac: Removed. |
| * aclocal.m4: Removed. |
| * configure: Removed. |
| |
| 2021-06-21 Mike Frysinger <vapier@gentoo.org> |
| |
| * aclocal.m4: Regenerate. |
| * configure: Regenerate. |
| |
| 2021-06-21 Mike Frysinger <vapier@gentoo.org> |
| |
| * configure: Regenerate. |
| |
| 2021-06-20 Mike Frysinger <vapier@gentoo.org> |
| |
| * configure.ac (SIM_AC_COMMON): Delete. |
| * aclocal.m4, configure: Regenerate. |
| |
| 2021-06-20 Mike Frysinger <vapier@gentoo.org> |
| |
| * aclocal.m4: Regenerate. |
| * configure: Regenerate. |
| |
| 2021-06-19 Mike Frysinger <vapier@gentoo.org> |
| |
| * aclocal.m4: Regenerate. |
| * configure: Regenerate. |
| |
| 2021-06-19 Mike Frysinger <vapier@gentoo.org> |
| |
| * configure: Regenerate. |
| |
| 2021-06-18 Mike Frysinger <vapier@gentoo.org> |
| |
| * aclocal.m4, configure: Regenerate. |
| |
| 2021-06-18 Mike Frysinger <vapier@gentoo.org> |
| |
| * configure: Regenerate. |
| |
| 2021-06-18 Mike Frysinger <vapier@gentoo.org> |
| |
| * cpustate.c: Include sim-signal.h. |
| * memory.c, simulator.c: Likewise. |
| |
| 2021-06-17 Mike Frysinger <vapier@gentoo.org> |
| |
| * configure.ac: Delete SIM_AC_OPTION_ENDIAN call. |
| * aclocal.m4, configure: Regenerate. |
| |
| 2021-06-16 Mike Frysinger <vapier@gentoo.org> |
| |
| * configure: Regenerate. |
| |
| 2021-06-16 Mike Frysinger <vapier@gentoo.org> |
| |
| * configure: Regenerate. |
| * config.in: Removed. |
| |
| 2021-06-15 Mike Frysinger <vapier@gentoo.org> |
| |
| * config.in, configure: Regenerate. |
| |
| 2021-06-14 Mike Frysinger <vapier@gentoo.org> |
| |
| * configure.ac: Delete call to SIM_AC_OPTION_WARNINGS. |
| * configure: Regenerate. |
| |
| 2021-06-12 Mike Frysinger <vapier@gentoo.org> |
| |
| * configure.ac: Delete call to SIM_AC_OPTION_ALIGNMENT. |
| * interp.c (sim_open): Set current_alignment. |
| |
| 2021-06-12 Mike Frysinger <vapier@gentoo.org> |
| |
| * aclocal.m4, config.in, configure: Regenerate. |
| |
| 2021-06-12 Mike Frysinger <vapier@gentoo.org> |
| |
| * config.in, configure: Regenerate. |
| |
| 2021-05-17 Mike Frysinger <vapier@gentoo.org> |
| |
| * sim-main.h (SIM_HAVE_COMMON_SIM_STATE): Delete. |
| |
| 2021-05-17 Mike Frysinger <vapier@gentoo.org> |
| |
| * sim-main.h (SIM_HAVE_COMMON_SIM_STATE): Define. |
| (struct sim_state): Delete. |
| |
| 2021-05-16 Mike Frysinger <vapier@gentoo.org> |
| |
| * cpustate.c: Include defs.h. |
| * interp.c: Replace config.h include with defs.h. |
| * memory.c, simulator.c: Likewise. |
| * cpustate.h, simulator.h: Delete config.h include. |
| |
| 2021-05-16 Mike Frysinger <vapier@gentoo.org> |
| |
| * config.in, configure: Regenerate. |
| |
| 2021-05-14 Mike Frysinger <vapier@gentoo.org> |
| |
| * cpustate.h: Update include path. |
| * interp.c: Likewise. |
| |
| 2021-05-04 Mike Frysinger <vapier@gentoo.org> |
| |
| * configure: Regenerate. |
| |
| 2021-05-01 Mike Frysinger <vapier@gentoo.org> |
| |
| * config.in, configure: Regenerate. |
| |
| 2021-05-01 Mike Frysinger <vapier@gentoo.org> |
| |
| * cpustate.c (aarch64_set_FP_float): Change lx to PRIx64. |
| (aarch64_set_FP_double, aarch64_set_FP_long_double, |
| aarch64_set_vec_u64, aarch64_set_vec_s64): Likewise. |
| |
| 2021-05-01 Mike Frysinger <vapier@gentoo.org> |
| |
| * simulator.c (do_fcvtzu): Change UL to ULL. |
| |
| 2021-04-26 Mike Frysinger <vapier@gentoo.org> |
| |
| * aclocal.m4, config.in, configure: Regenerate. |
| |
| 2021-04-22 Tom Tromey <tom@tromey.com> |
| |
| * configure, config.in: Rebuild. |
| |
| 2021-04-22 Tom Tromey <tom@tromey.com> |
| |
| * configure: Rebuild. |
| |
| 2021-04-21 Mike Frysinger <vapier@gentoo.org> |
| |
| * aclocal.m4: Regenerate. |
| |
| 2021-04-21 Simon Marchi <simon.marchi@polymtl.ca> |
| |
| * configure: Regenerate. |
| |
| 2021-04-18 Mike Frysinger <vapier@gentoo.org> |
| |
| * configure: Regenerate. |
| |
| 2021-04-12 Mike Frysinger <vapier@gentoo.org> |
| |
| * interp.c (sim_open): Delete 3rd arg to sim_cpu_alloc_all. |
| |
| 2021-04-07 Jim Wilson <jimw@sifive.com> |
| |
| PR sim/27483 |
| * simulator.c (set_flags_for_add32): Compare uresult against |
| itself. Compare sresult against itself. |
| |
| 2021-04-02 Mike Frysinger <vapier@gentoo.org> |
| |
| * aclocal.m4, configure: Regenerate. |
| |
| 2021-02-28 Mike Frysinger <vapier@gentoo.org> |
| |
| * configure: Regenerate. |
| |
| 2021-02-21 Mike Frysinger <vapier@gentoo.org> |
| |
| * configure.ac (AC_CONFIG_MACRO_DIRS): Replace common with m4. |
| * aclocal.m4, configure: Regenerate. |
| |
| 2021-02-13 Mike Frysinger <vapier@gentoo.org> |
| |
| * configure.ac: Replace sinclude with AC_CONFIG_MACRO_DIRS. |
| * aclocal.m4, configure: Regenerate. |
| |
| 2021-02-06 Mike Frysinger <vapier@gentoo.org> |
| |
| * configure: Regenerate. |
| |
| 2021-01-11 Mike Frysinger <vapier@gentoo.org> |
| |
| * config.in, configure: Regenerate. |
| |
| 2021-01-09 Mike Frysinger <vapier@gentoo.org> |
| |
| * configure: Regenerate. |
| |
| 2021-01-08 Mike Frysinger <vapier@gentoo.org> |
| |
| * configure: Regenerate. |
| |
| 2021-01-04 Mike Frysinger <vapier@gentoo.org> |
| |
| * configure: Regenerate. |
| |
| 2020-02-06 Carlo Bramini <carlo_bramini@users.sourceforge.net> |
| |
| PR sim/25318 |
| * simulator.c (blr): Read destination register before calling |
| aarch64_save_LR. |
| |
| 2019-03-28 Andrew Burgess <andrew.burgess@embecosm.com> |
| |
| * cpustate.c: Add 'libiberty.h' include. |
| * interp.c: Add 'sim-assert.h' include. |
| |
| 2017-09-06 John Baldwin <jhb@FreeBSD.org> |
| |
| * configure: Regenerate. |
| |
| 2017-04-22 Jim Wilson <jim.wilson@linaro.org> |
| |
| * simulator.c (vec_load): Add M argument. Rewrite to iterate over |
| registers based on structure size. |
| (LD4, LD3, LD2, LD1_2, LD1_3, LD1_4): Pass new arg to vec_load. |
| (LD1_1): Replace with call to vec_load. |
| (vec_store): Add new M argument. Rewrite to iterate over registers |
| based on structure size. |
| (ST4, ST3, ST2, ST1_2, ST1_3, ST1_4): Pass new arg to vec_store. |
| (ST1_1): Replace with call to vec_store. |
| |
| 2017-04-08 Jim Wilson <jim.wilson@linaro.org> |
| |
| * simulator.c (do_vec_FCVTL): New. |
| (do_vec_op1): Call do_vec_FCVTL. |
| |
| * simulator.c (do_scalar_FCMGE_zero, do_scalar_FCMLE_zero, |
| do_scalar_FCMGT_zero, do_scalar_FCMEQ_zero, do_scalar_FCMLT_zero): New. |
| (do_scalar_vec): Add calls to new functions. |
| |
| 2017-03-25 Jim Wilson <jim.wilson@linaro.org> |
| |
| * simulator.c (set_flags_for_add32): Cast result to uint32_t in carry |
| flag check. |
| |
| 2017-03-03 Jim Wilson <jim.wilson@linaro.org> |
| |
| * simulator.c (mul64hi): Shift carry left by 32. |
| (smulh): Change signum to negate. If negate, invert result, and add |
| carry bit if low part of multiply result is zero. |
| |
| 2017-02-25 Jim Wilson <jim.wilson@linaro.org> |
| |
| * simulator.c (do_vec_SMOV_into_scalar): New. |
| (do_vec_UMOV_into_scalar): Renamed from do_vec_MOV_into_scalar. |
| Rewritten. |
| (do_vec_UMOV): Merged into do_vec_UMOV_into_scalar and deleted. |
| (do_vec_op1): Move do_vec_TRN call and do_vec_UZP call. Add |
| do_vec_SMOV_into_scalar call. Delete do_vec_MOV_into_scalar and |
| do_vec_UMOV calls. Add do_vec_UMOV_into_scalar call. |
| |
| * simulator.c (popcount): New. |
| (do_vec_CNT): New. |
| (do_vec_op1): Add do_vec_CNT call. |
| |
| 2017-02-19 Jim Wilson <jim.wilson@linaro.org> |
| |
| * simulator.c (do_vec_ADDV): Mov val declaration inside each case, |
| with type set to input type size. |
| (do_vec_xtl): Change bias from 3 to 4 for byte case. |
| |
| 2017-02-14 Jim Wilson <jim.wilson@linaro.org> |
| |
| * simulator.c (do_vec_MLA): Rewrite switch body. |
| |
| * simulator.c (do_vec_bit): Change loop limits from 16 and 8 to 4 and |
| 2. Move test_false if inside loop. Fix logic for computing result |
| stored to vd. |
| |
| * simulator.c: (LDn_STn_SINGLE_LANE_AND_SIZE): New. |
| (do_vec_LDn_single, do_vec_STn_single): New. |
| (do_vec_LDnR): Add and set new nregs var. Replace switch on nregs with |
| loop over nregs using new var n. Add n times size to address in loop. |
| Add n to vd in loop. |
| (do_vec_load_store): Add comment for instruction bit 24. New var |
| single to hold instruction bit 24. Add new code to use single. Move |
| ldnr support inside single if statements. Fix ldnr register counts |
| inside post if statement. Change HALT_NYI calls to HALT_UNALLOC. |
| |
| 2017-01-23 Jim Wilson <jim.wilson@linaro.org> |
| |
| * simulator.c (do_vec_compare): Add case 0x23 for CMTST. |
| |
| 2017-01-17 Jim Wilson <jim.wilson@linaro.org> |
| |
| * simulator.c (do_vec_ADDV): Call aarch64_set_vec_u64 instead of |
| aarch64_set_reg_u64. In case 2, call HALT_UNALLOC if not full. In |
| case 3, call HALT_UNALLOC unconditionally. |
| (do_vec_XTN): Delete shifts. In case 2, change index from i + 4 to |
| i + 2. Delete if on bias, change index to i + bias * X. |
| |
| 2017-01-09 Jim Wilson <jim.wilson@linaro.org> |
| |
| * simulator.c (do_vec_UZP): Rewrite. |
| |
| 2017-01-04 Jim Wilson <jim.wilson@linaro.org> |
| |
| * cpustate.c: Include math.h. |
| (aarch64_set_FP_float): Use signbit to check for signed zero. |
| (aarch64_set_FP_double): Likewise. |
| * simulator.c (do_vec_MOV_immediate, case 0x8): Add missing break. |
| (do_vec_mul): In all DO_VEC_WIDENING_MUL calls, make second and fourth |
| args same size as third arg. |
| (fmaxnm): Use isnan instead of fpclassify. |
| (fminnm, dmaxnm, dminnm): Likewise. |
| (do_vec_MLS): Reverse order of subtraction operands. |
| (dexSimpleFPCondSelect): Call aarch64_get_FP_double or |
| aarch64_get_FP_float to get source register contents. |
| (UINT_MIN, ULONG_MIN, FLOAT_UINT_MAX, FLOAT_UINT_MIN, |
| DOUBLE_UINT_MAX, DOUBLE_UINT_MIN, FLOAT_ULONG_MAX, FLOAT_ULONG_MIN, |
| DOUBLE_ULONG_MAX, DOUBLE_ULONG_MIN): New. |
| (do_fcvtzu): Use ULONG instead of LONG, and UINT instead of INT in |
| raise_exception calls. |
| |
| 2016-12-21 Jim Wilson <jim.wilson@linaro.org> |
| |
| * simulator.c (set_flags_for_float_compare): Add code to handle Inf. |
| Add comment to document NaN issue. |
| (set_flags_for_double_compare): Likewise. |
| |
| 2016-12-13 Jim Wilson <jim.wilson@linaro.org> |
| |
| * simulator.c (NEG, POS): Move before set_flags_for_add64. |
| (set_flags_for_add64): Replace with a modified copy of |
| set_flags_for_sub64. |
| |
| 2016-12-03 Jim Wilson <jim.wilson@linaro.org> |
| |
| * simulator.c (tbnz, tbz): Cast 1 to uint64_t before shifting. |
| (dexTestBranchImmediate): Shift high bit of pos by 5 not 4. |
| |
| 2016-12-01 Jim Wilson <jim.wilson@linaro.org> |
| |
| * simulator.c (fsturs): Switch use of rn and st variables. |
| (fsturd, fsturq): Likewise |
| |
| 2016-08-15 Mike Frysinger <vapier@gentoo.org> |
| |
| * interp.c: Include bfd.h. |
| (symcount, symtab, aarch64_get_sym_value): Delete. |
| (remove_useless_symbols): Change count type to long. |
| (aarch64_get_func): Add SIM_DESC to arg list. Add symcount |
| and symtab local variables. |
| (sim_create_inferior): Delete storage. Replace symbol code |
| with a call to trace_load_symbols. |
| * memory.c: Delete bfd.h, elf/internal.h, and elf/common.h |
| includes. |
| (aarch64_get_heap_start): Change aarch64_get_sym_value to |
| trace_sym_value. |
| * memory.h: Delete bfd.h include. |
| (mem_add_blk): Delete unused prototype. |
| * simulator.c (bl, blr): Pass SIM_DESC to aarch64_get_func. |
| * simulator.c (aarch64_get_func): Add SIM_DESC to arg list. |
| (aarch64_get_sym_value): Delete. |
| |
| 2016-08-12 Nick Clifton <nickc@redhat.com> |
| |
| * simulator.c (aarch64_step): Revert pervious delta. |
| (aarch64_run): Call sim_events_tick after each |
| instruction is simulated, and if necessary call |
| sim_events_process. |
| * simulator.h: Revert previous delta. |
| |
| 2016-08-11 Nick Clifton <nickc@redhat.com> |
| |
| * interp.c (sim_create_inferior): Allow for being called with a |
| NULL abfd parameter. If a bfd is provided, initialise the sim |
| with that start address. |
| * simulator.c (HALT_NYI): Just print out the numeric value of the |
| instruction when not tracing. |
| (aarch64_step): Change from static to global. |
| * simulator.h: Add a prototype for aarch64_step(). |
| |
| 2016-07-27 Alan Modra <amodra@gmail.com> |
| |
| * memory.c: Don't include libbfd.h. |
| |
| 2016-07-21 Nick Clifton <nickc@redhat.com> |
| |
| * simulator.c (fsqrts): Use sqrtf rather than sqrt. |
| |
| 2016-06-30 Jim Wilson <jim.wilson@linaro.org> |
| |
| * cpustate.h: Include config.h. |
| (union GRegisterValue): Add WORDS_BIGENDIAN check. For big endian code |
| use anonymous structs to align members. |
| * simulator.c (aarch64_step): Use sim_core_read_buffer and |
| endian_le2h_4 to read instruction from pc. |
| |
| 2016-05-06 Nick Clifton <nickc@redhat.com> |
| |
| * simulator.c (do_FMLA_by_element): New function. |
| (do_vec_op2): Call it. |
| |
| 2016-04-27 Nick Clifton <nickc@redhat.com> |
| |
| * simulator.c: Add TRACE_DECODE statements to all emulation |
| functions. |
| |
| 2016-03-30 Nick Clifton <nickc@redhat.com> |
| |
| * cpustate.c (aarch64_set_reg_s32): New function. |
| (aarch64_set_reg_u32): New function. |
| (aarch64_get_FP_half): Place half precision value into the correct |
| slot of the union. |
| (aarch64_set_FP_half): Likewise. |
| * cpustate.h: Add prototypes for aarch64_set_reg_s32 and |
| aarch64_set_reg_u32. |
| * memory.c (FETCH_FUNC): Cast the read value to the access type |
| before converting it to the return type. Rename to FETCH_FUNC64. |
| (FETCH_FUNC32): New macro. Duplicates FETCH_FUNC64 but for 32-bit |
| accesses. Use for 32-bit memory access functions. |
| * simulator.c (ldrsb_wb): Use sign extension not zero extension. |
| (ldrb_scale_ext, ldrsh32_abs, ldrsh32_wb): Likewise. |
| (ldrsh32_scale_ext, ldrsh_abs, ldrsh64_wb): Likewise. |
| (ldrsh_scale_ext, ldrsw_abs): Likewise. |
| (ldrh32_abs): Store 32 bit value not 64-bits. |
| (ldrh32_wb, ldrh32_scale_ext): Likewise. |
| (do_vec_MOV_immediate): Fix computation of val. |
| (do_vec_MVNI): Likewise. |
| (DO_VEC_WIDENING_MUL): New macro. |
| (do_vec_mull): Use new macro. |
| (do_vec_mul): Use new macro. |
| (do_vec_MLA): Read values before writing. |
| (do_vec_xtl): Likewise. |
| (do_vec_SSHL): Select correct shift value. |
| (do_vec_USHL): Likewise. |
| (do_scalar_UCVTF): New function. |
| (do_scalar_vec): Call new function. |
| (store_pair_u64): Treat reads of SP as reads of XZR. |
| |
| 2016-03-29 Nick Clifton <nickc@redhat.com> |
| |
| * cpustate.c: Remove space after asterisk in function parameters. |
| * decode.h (greg): Delete unused function. |
| (vreg, shift, extension, scaling, writeback, condcode): Likewise. |
| * simulator.c: Use INSTR macro in more places. |
| (HALT_NYI): Use sim_io_eprintf in place of fprintf. |
| Remove extraneous whitespace. |
| |
| 2016-03-23 Nick Clifton <nickc@redhat.com> |
| |
| * cpustate.c (aarch64_get_FP_half): New function. Read a vector |
| register as a half precision floating point number. |
| (aarch64_set_FP_half): New function. Similar, but for setting |
| a half precision register. |
| (aarch64_get_thread_id): New function. Returns the value of the |
| CPU's TPIDR register. |
| (aarch64_get_FPCR): New function. Returns the value of the CPU's |
| floating point control register. |
| (aarch64_set_FPCR): New function. Set the value of the CPU's FPCR |
| register. |
| * cpustate.h: Add prototypes for new functions. |
| * sim-main.h (struct _sim_cpu): Add FPCR and tpidr fields. |
| * memory.c: Use unaligned core access functions for all memory |
| reads and writes. |
| * simulator.c (HALT_NYI): Generate an error message if tracing |
| will not tell the user why the simulator is halting. |
| (HALT_UNREACHABLE): Delete. Delete (unneeded) uses of the macro. |
| (INSTR): New time-saver macro. |
| (fldrb_abs): New function. Loads an 8-bit value using a scaled |
| offset. |
| (fldrh_abs): New function. Likewise for 16-bit values. |
| (do_vec_SSHL): Allow for negative shift values. |
| (do_vec_USHL): Likewise. |
| (do_vec_SHL): Correct computation of shift amount. |
| (do_vec_SSHR_USHR): Correct decision of signed vs unsigned |
| shifts and computation of shift value. |
| (clz): New function. Counts leading zero bits. |
| (do_vec_CLZ): New function. Implements CLZ (vector). |
| (do_vec_MOV_element): Call do_vec_CLZ. |
| (dexSimpleFPCondCompare): Implement. |
| (do_FCVT_half_to_single): New function. Implements one of the |
| FCVT operations. |
| (do_FCVT_half_to_double): New function. Likewise. |
| (do_FCVT_single_to_half): New function. Likewise. |
| (do_FCVT_double_to_half): New function. Likewise. |
| (dexSimpleFPDataProc1Source): Call new FCVT functions. |
| (do_scalar_SHL): Handle negative shifts. |
| (do_scalar_shift): Handle SSHR. |
| (do_scalar_USHL): New function. |
| (do_double_add): Simplify to just performing a double precision |
| add operation. Move remaining code into... |
| (do_scalar_vec): ... New function. |
| (dexLoadUnsignedImmediate): Call new fldrb_abs and fldrh_abs |
| functions. |
| (system_get): Add support for TPIDR, CTR, FPCR, FPSR and CPSR |
| registers. |
| (system_set): New function. |
| (do_MSR_immediate): New function. Stub for now. |
| (do_MSR_reg): New function. Likewise. Partially implements MSR |
| instruction. |
| (do_SYS): New function. Stub for now, |
| (dexSystem): Call new functions. |
| |
| 2016-03-18 Nick Clifton <nickc@redhat.com> |
| |
| * cpustate.c: Remove spurious spaces from TRACE strings. |
| Print hex equivalents of floats and doubles. |
| Check element number against array size when accessing vector |
| registers. |
| (GET_VEC_ELEMENT): Fix off by one error checking for an invalid |
| element index. |
| (SET_VEC_ELEMENT): Likewise. |
| (GET_VEC_ELEMENT): And fix thinko using macro arguments. |
| |
| * memory.c: Trace memory reads when --trace-memory is enabled. |
| Remove float and double load and store functions. |
| * memory.h (aarch64_get_mem_float): Delete prototype. |
| (aarch64_get_mem_double): Likewise. |
| (aarch64_set_mem_float): Likewise. |
| (aarch64_set_mem_double): Likewise. |
| * simulator (IS_SET): Always return either 0 or 1. |
| (IS_CLEAR): Likewise. |
| (fldrs_pcrel): Load and store floats using 32-bit memory accesses |
| and doubles using 64-bit memory accesses. |
| (fldrd_pcrel, fldrs_wb, fldrs_abs, fldrs_scale_ext): Likewise. |
| (fldrd_wb, fldrd_abs, fsturs, fsturd, fldurs, fldurd): Likewise. |
| (fstrs_abs, fstrs_wb, fstrs_scale_ext, fstrd_abs): Likewise. |
| (fstrd_wb, fstrd_scale_ext, store_pair_float): Likewise. |
| (store_pair_double, load_pair_float, load_pair_double): Likewise. |
| (do_vec_MUL_by_element): New function. |
| (do_vec_op2): Call do_vec_MUL_by_element. |
| (do_scalar_NEG): New function. |
| (do_double_add): Call do_scalar_NEG. |
| |
| 2016-03-03 Nick Clifton <nickc@redhat.com> |
| |
| * simulator.c (set_flags_for_sub32): Correct type of signbit. |
| (CondCompare): Swap interpretation of bit 30. |
| (DO_ADDP): Delete macro. |
| (do_vec_ADDP): Copy source registers before starting to update |
| destination register. |
| (do_vec_FADDP): Likewise. |
| (do_vec_load_store): Fix computation of sizeof_operation. |
| (rbit64): Fix type of constant. |
| (aarch64_step): When displaying insn value, display all 32 bits. |
| |
| 2016-01-10 Mike Frysinger <vapier@gentoo.org> |
| |
| * config.in, configure: Regenerate. |
| |
| 2016-01-10 Mike Frysinger <vapier@gentoo.org> |
| |
| * configure: Regenerate. |
| |
| 2016-01-10 Mike Frysinger <vapier@gentoo.org> |
| |
| * configure.ac (SIM_AC_OPTION_ENVIRONMENT): Delete call. |
| * configure: Regenerate. |
| |
| 2016-01-10 Mike Frysinger <vapier@gentoo.org> |
| |
| * configure: Regenerate. |
| |
| 2016-01-10 Mike Frysinger <vapier@gentoo.org> |
| |
| * configure: Regenerate. |
| |
| 2016-01-10 Mike Frysinger <vapier@gentoo.org> |
| |
| * configure.ac (SIM_AC_OPTION_INLINE): Delete call. |
| * configure: Regenerate. |
| |
| 2016-01-10 Mike Frysinger <vapier@gentoo.org> |
| |
| * configure: Regenerate. |
| |
| 2016-01-10 Mike Frysinger <vapier@gentoo.org> |
| |
| * configure: Regenerate. |
| |
| 2016-01-09 Mike Frysinger <vapier@gentoo.org> |
| |
| * config.in, configure: Regenerate. |
| |
| 2016-01-06 Mike Frysinger <vapier@gentoo.org> |
| |
| * interp.c (sim_create_inferior): Mark argv and env const. |
| (sim_open): Mark argv const. |
| |
| 2016-01-05 Mike Frysinger <vapier@gentoo.org> |
| |
| * interp.c: Delete dis-asm.h include. |
| (info, opbuf, op_printf, aarch64_print_insn, sim_dis_read): Delete. |
| (sim_create_inferior): Delete disassemble init logic. |
| (OPTION_DISAS, aarch64_option_handler, aarch64_options): Delete. |
| (sim_open): Delete sim_add_option_table call. |
| * memory.c (mem_error): Delete disas check. |
| * simulator.c: Delete dis-asm.h include. |
| (disas): Delete. |
| (HALT_UNALLOC): Replace disassembly logic with TRACE_DISASM. |
| (HALT_NYI): Likewise. |
| (handle_halt): Delete disas call. |
| (aarch64_step): Replace disas logic with TRACE_DISASM. |
| * simulator.h: Delete dis-asm.h include. |
| (aarch64_print_insn): Delete. |
| |
| 2016-01-04 Mike Frysinger <vapier@gentoo.org> |
| |
| * simulator.c (MAX, MIN): Delete. |
| (do_vec_maxv): Change MAX to max and MIN to min. |
| (do_vec_fminmaxV): Likewise. |
| |
| 2016-01-04 Tristan Gingold <gingold@adacore.com> |
| |
| * simulator.c: Remove syscall.h include. |
| |
| 2016-01-04 Mike Frysinger <vapier@gentoo.org> |
| |
| * configure: Regenerate. |
| |
| 2016-01-03 Mike Frysinger <vapier@gentoo.org> |
| |
| * configure.ac (SIM_AC_OPTION_HOSTENDIAN): Delete. |
| * configure: Regenerate. |
| |
| 2016-01-02 Mike Frysinger <vapier@gentoo.org> |
| |
| * configure: Regenerate. |
| |
| 2015-12-27 Mike Frysinger <vapier@gentoo.org> |
| |
| * interp.c (sim_dis_read): Change private_data to application_data. |
| (sim_create_inferior): Likewise. |
| |
| 2015-12-27 Mike Frysinger <vapier@gentoo.org> |
| |
| * Makefile.in (SIM_OBJS): Delete sim-hload.o. |
| |
| 2015-12-26 Mike Frysinger <vapier@gentoo.org> |
| |
| * config.in, configure: Regenerate. |
| |
| 2015-12-26 Mike Frysinger <vapier@gentoo.org> |
| |
| * interp.c (sim_create_inferior): Update comment and argv check. |
| |
| 2015-12-14 Nick Clifton <nickc@redhat.com> |
| |
| * simulator.c (system_get): New function. Provides read |
| access to the dczid system register. |
| (do_mrs): New function - implements the MRS instruction. |
| (dexSystem): Call do_mrs for the MRS instruction. Halt on |
| unimplemented system instructions. |
| |
| 2015-11-24 Nick Clifton <nickc@redhat.com> |
| |
| * configure.ac: New configure template. |
| * aclocal.m4: Generate. |
| * config.in: Generate. |
| * configure: Generate. |
| * cpustate.c: New file - functions for accessing AArch64 registers. |
| * cpustate.h: New header. |
| * decode.h: New header. |
| * interp.c: New file - interface between GDB and simulator. |
| * Makefile.in: New makefile template. |
| * memory.c: New file - functions for simulating aarch64 memory |
| accesses. |
| * memory.h: New header. |
| * sim-main.h: New header. |
| * simulator.c: New file - aarch64 simulator functions. |
| * simulator.h: New header. |
