| /* Simulator model support for m32rbf. |
| |
| THIS FILE IS MACHINE GENERATED WITH CGEN. |
| |
| Copyright (C) 1996-2024 Free Software Foundation, Inc. |
| |
| This file is part of the GNU simulators. |
| |
| This file is free software; you can redistribute it and/or modify |
| it under the terms of the GNU General Public License as published by |
| the Free Software Foundation; either version 3, or (at your option) |
| any later version. |
| |
| It is distributed in the hope that it will be useful, but WITHOUT |
| ANY WARRANTY; without even the implied warranty of MERCHANTABILITY |
| or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public |
| License for more details. |
| |
| You should have received a copy of the GNU General Public License along |
| with this program; if not, write to the Free Software Foundation, Inc., |
| 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. |
| |
| */ |
| |
| #define WANT_CPU m32rbf |
| #define WANT_CPU_M32RBF |
| |
| #include "sim-main.h" |
| |
| /* The profiling data is recorded here, but is accessed via the profiling |
| mechanism. After all, this is information for profiling. */ |
| |
| #if WITH_PROFILE_MODEL_P |
| |
| /* Model handlers for each insn. */ |
| |
| static int |
| model_m32r_d_add (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_add.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| INT in_dr = -1; |
| INT out_dr = -1; |
| in_sr = FLD (in_sr); |
| in_dr = FLD (in_dr); |
| out_dr = FLD (out_dr); |
| referenced |= 1 << 0; |
| referenced |= 1 << 1; |
| referenced |= 1 << 2; |
| cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r_d_add3 (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_add3.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| INT in_dr = -1; |
| INT out_dr = -1; |
| in_sr = FLD (in_sr); |
| out_dr = FLD (out_dr); |
| referenced |= 1 << 0; |
| referenced |= 1 << 2; |
| cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r_d_and (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_add.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| INT in_dr = -1; |
| INT out_dr = -1; |
| in_sr = FLD (in_sr); |
| in_dr = FLD (in_dr); |
| out_dr = FLD (out_dr); |
| referenced |= 1 << 0; |
| referenced |= 1 << 1; |
| referenced |= 1 << 2; |
| cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r_d_and3 (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_and3.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| INT in_dr = -1; |
| INT out_dr = -1; |
| in_sr = FLD (in_sr); |
| out_dr = FLD (out_dr); |
| referenced |= 1 << 0; |
| referenced |= 1 << 2; |
| cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r_d_or (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_add.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| INT in_dr = -1; |
| INT out_dr = -1; |
| in_sr = FLD (in_sr); |
| in_dr = FLD (in_dr); |
| out_dr = FLD (out_dr); |
| referenced |= 1 << 0; |
| referenced |= 1 << 1; |
| referenced |= 1 << 2; |
| cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r_d_or3 (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_and3.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| INT in_dr = -1; |
| INT out_dr = -1; |
| in_sr = FLD (in_sr); |
| out_dr = FLD (out_dr); |
| referenced |= 1 << 0; |
| referenced |= 1 << 2; |
| cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r_d_xor (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_add.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| INT in_dr = -1; |
| INT out_dr = -1; |
| in_sr = FLD (in_sr); |
| in_dr = FLD (in_dr); |
| out_dr = FLD (out_dr); |
| referenced |= 1 << 0; |
| referenced |= 1 << 1; |
| referenced |= 1 << 2; |
| cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r_d_xor3 (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_and3.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| INT in_dr = -1; |
| INT out_dr = -1; |
| in_sr = FLD (in_sr); |
| out_dr = FLD (out_dr); |
| referenced |= 1 << 0; |
| referenced |= 1 << 2; |
| cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r_d_addi (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_addi.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| INT in_dr = -1; |
| INT out_dr = -1; |
| in_dr = FLD (in_dr); |
| out_dr = FLD (out_dr); |
| referenced |= 1 << 1; |
| referenced |= 1 << 2; |
| cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r_d_addv (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_add.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| INT in_dr = -1; |
| INT out_dr = -1; |
| in_sr = FLD (in_sr); |
| in_dr = FLD (in_dr); |
| out_dr = FLD (out_dr); |
| referenced |= 1 << 0; |
| referenced |= 1 << 1; |
| referenced |= 1 << 2; |
| cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r_d_addv3 (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_add3.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| INT in_dr = -1; |
| INT out_dr = -1; |
| in_sr = FLD (in_sr); |
| out_dr = FLD (out_dr); |
| referenced |= 1 << 0; |
| referenced |= 1 << 2; |
| cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r_d_addx (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_add.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| INT in_dr = -1; |
| INT out_dr = -1; |
| in_sr = FLD (in_sr); |
| in_dr = FLD (in_dr); |
| out_dr = FLD (out_dr); |
| referenced |= 1 << 0; |
| referenced |= 1 << 1; |
| referenced |= 1 << 2; |
| cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r_d_bc8 (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_bl8.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| if (insn_referenced & (1 << 2)) referenced |= 1 << 1; |
| cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, in_sr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r_d_bc24 (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_bl24.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| if (insn_referenced & (1 << 2)) referenced |= 1 << 1; |
| cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, in_sr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r_d_beq (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_beq.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| if (insn_referenced & (1 << 3)) referenced |= 1 << 1; |
| cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, in_sr); |
| } |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_src1 = -1; |
| INT in_src2 = -1; |
| in_src1 = FLD (in_src1); |
| in_src2 = FLD (in_src2); |
| referenced |= 1 << 0; |
| referenced |= 1 << 1; |
| cycles += m32rbf_model_m32r_d_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r_d_beqz (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_beq.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| if (insn_referenced & (1 << 2)) referenced |= 1 << 1; |
| cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, in_sr); |
| } |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_src1 = -1; |
| INT in_src2 = -1; |
| in_src2 = FLD (in_src2); |
| referenced |= 1 << 1; |
| cycles += m32rbf_model_m32r_d_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r_d_bgez (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_beq.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| if (insn_referenced & (1 << 2)) referenced |= 1 << 1; |
| cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, in_sr); |
| } |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_src1 = -1; |
| INT in_src2 = -1; |
| in_src2 = FLD (in_src2); |
| referenced |= 1 << 1; |
| cycles += m32rbf_model_m32r_d_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r_d_bgtz (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_beq.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| if (insn_referenced & (1 << 2)) referenced |= 1 << 1; |
| cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, in_sr); |
| } |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_src1 = -1; |
| INT in_src2 = -1; |
| in_src2 = FLD (in_src2); |
| referenced |= 1 << 1; |
| cycles += m32rbf_model_m32r_d_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r_d_blez (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_beq.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| if (insn_referenced & (1 << 2)) referenced |= 1 << 1; |
| cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, in_sr); |
| } |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_src1 = -1; |
| INT in_src2 = -1; |
| in_src2 = FLD (in_src2); |
| referenced |= 1 << 1; |
| cycles += m32rbf_model_m32r_d_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r_d_bltz (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_beq.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| if (insn_referenced & (1 << 2)) referenced |= 1 << 1; |
| cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, in_sr); |
| } |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_src1 = -1; |
| INT in_src2 = -1; |
| in_src2 = FLD (in_src2); |
| referenced |= 1 << 1; |
| cycles += m32rbf_model_m32r_d_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r_d_bnez (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_beq.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| if (insn_referenced & (1 << 2)) referenced |= 1 << 1; |
| cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, in_sr); |
| } |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_src1 = -1; |
| INT in_src2 = -1; |
| in_src2 = FLD (in_src2); |
| referenced |= 1 << 1; |
| cycles += m32rbf_model_m32r_d_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r_d_bl8 (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_bl8.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| referenced |= 1 << 1; |
| cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, in_sr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r_d_bl24 (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_bl24.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| referenced |= 1 << 1; |
| cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, in_sr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r_d_bnc8 (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_bl8.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| if (insn_referenced & (1 << 2)) referenced |= 1 << 1; |
| cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, in_sr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r_d_bnc24 (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_bl24.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| if (insn_referenced & (1 << 2)) referenced |= 1 << 1; |
| cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, in_sr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r_d_bne (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_beq.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| if (insn_referenced & (1 << 3)) referenced |= 1 << 1; |
| cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, in_sr); |
| } |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_src1 = -1; |
| INT in_src2 = -1; |
| in_src1 = FLD (in_src1); |
| in_src2 = FLD (in_src2); |
| referenced |= 1 << 0; |
| referenced |= 1 << 1; |
| cycles += m32rbf_model_m32r_d_u_cmp (current_cpu, idesc, 1, referenced, in_src1, in_src2); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r_d_bra8 (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_bl8.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| referenced |= 1 << 1; |
| cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, in_sr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r_d_bra24 (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_bl24.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| referenced |= 1 << 1; |
| cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, in_sr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r_d_cmp (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_st_plus.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_src1 = -1; |
| INT in_src2 = -1; |
| in_src1 = FLD (in_src1); |
| in_src2 = FLD (in_src2); |
| referenced |= 1 << 0; |
| referenced |= 1 << 1; |
| cycles += m32rbf_model_m32r_d_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r_d_cmpi (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_st_d.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_src1 = -1; |
| INT in_src2 = -1; |
| in_src2 = FLD (in_src2); |
| referenced |= 1 << 1; |
| cycles += m32rbf_model_m32r_d_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r_d_cmpu (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_st_plus.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_src1 = -1; |
| INT in_src2 = -1; |
| in_src1 = FLD (in_src1); |
| in_src2 = FLD (in_src2); |
| referenced |= 1 << 0; |
| referenced |= 1 << 1; |
| cycles += m32rbf_model_m32r_d_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r_d_cmpui (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_st_d.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_src1 = -1; |
| INT in_src2 = -1; |
| in_src2 = FLD (in_src2); |
| referenced |= 1 << 1; |
| cycles += m32rbf_model_m32r_d_u_cmp (current_cpu, idesc, 0, referenced, in_src1, in_src2); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r_d_div (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_add.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| INT in_dr = -1; |
| INT out_dr = -1; |
| in_sr = FLD (in_sr); |
| in_dr = FLD (in_dr); |
| out_dr = FLD (out_dr); |
| referenced |= 1 << 0; |
| if (insn_referenced & (1 << 0)) referenced |= 1 << 1; |
| if (insn_referenced & (1 << 2)) referenced |= 1 << 2; |
| cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r_d_divu (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_add.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| INT in_dr = -1; |
| INT out_dr = -1; |
| in_sr = FLD (in_sr); |
| in_dr = FLD (in_dr); |
| out_dr = FLD (out_dr); |
| referenced |= 1 << 0; |
| if (insn_referenced & (1 << 0)) referenced |= 1 << 1; |
| if (insn_referenced & (1 << 2)) referenced |= 1 << 2; |
| cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r_d_rem (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_add.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| INT in_dr = -1; |
| INT out_dr = -1; |
| in_sr = FLD (in_sr); |
| in_dr = FLD (in_dr); |
| out_dr = FLD (out_dr); |
| referenced |= 1 << 0; |
| if (insn_referenced & (1 << 0)) referenced |= 1 << 1; |
| if (insn_referenced & (1 << 2)) referenced |= 1 << 2; |
| cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r_d_remu (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_add.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| INT in_dr = -1; |
| INT out_dr = -1; |
| in_sr = FLD (in_sr); |
| in_dr = FLD (in_dr); |
| out_dr = FLD (out_dr); |
| referenced |= 1 << 0; |
| if (insn_referenced & (1 << 0)) referenced |= 1 << 1; |
| if (insn_referenced & (1 << 2)) referenced |= 1 << 2; |
| cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r_d_jl (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_jl.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| in_sr = FLD (in_sr); |
| referenced |= 1 << 0; |
| referenced |= 1 << 1; |
| cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, in_sr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r_d_jmp (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_jl.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| in_sr = FLD (in_sr); |
| referenced |= 1 << 0; |
| referenced |= 1 << 1; |
| cycles += m32rbf_model_m32r_d_u_cti (current_cpu, idesc, 0, referenced, in_sr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r_d_ld (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_ld_plus.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = 0; |
| INT out_dr = 0; |
| in_sr = FLD (in_sr); |
| out_dr = FLD (out_dr); |
| referenced |= 1 << 0; |
| referenced |= 1 << 1; |
| cycles += m32rbf_model_m32r_d_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r_d_ld_d (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_add3.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = 0; |
| INT out_dr = 0; |
| in_sr = FLD (in_sr); |
| out_dr = FLD (out_dr); |
| referenced |= 1 << 0; |
| referenced |= 1 << 1; |
| cycles += m32rbf_model_m32r_d_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r_d_ldb (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_ld_plus.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = 0; |
| INT out_dr = 0; |
| in_sr = FLD (in_sr); |
| out_dr = FLD (out_dr); |
| referenced |= 1 << 0; |
| referenced |= 1 << 1; |
| cycles += m32rbf_model_m32r_d_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r_d_ldb_d (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_add3.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = 0; |
| INT out_dr = 0; |
| in_sr = FLD (in_sr); |
| out_dr = FLD (out_dr); |
| referenced |= 1 << 0; |
| referenced |= 1 << 1; |
| cycles += m32rbf_model_m32r_d_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r_d_ldh (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_ld_plus.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = 0; |
| INT out_dr = 0; |
| in_sr = FLD (in_sr); |
| out_dr = FLD (out_dr); |
| referenced |= 1 << 0; |
| referenced |= 1 << 1; |
| cycles += m32rbf_model_m32r_d_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r_d_ldh_d (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_add3.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = 0; |
| INT out_dr = 0; |
| in_sr = FLD (in_sr); |
| out_dr = FLD (out_dr); |
| referenced |= 1 << 0; |
| referenced |= 1 << 1; |
| cycles += m32rbf_model_m32r_d_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r_d_ldub (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_ld_plus.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = 0; |
| INT out_dr = 0; |
| in_sr = FLD (in_sr); |
| out_dr = FLD (out_dr); |
| referenced |= 1 << 0; |
| referenced |= 1 << 1; |
| cycles += m32rbf_model_m32r_d_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r_d_ldub_d (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_add3.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = 0; |
| INT out_dr = 0; |
| in_sr = FLD (in_sr); |
| out_dr = FLD (out_dr); |
| referenced |= 1 << 0; |
| referenced |= 1 << 1; |
| cycles += m32rbf_model_m32r_d_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r_d_lduh (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_ld_plus.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = 0; |
| INT out_dr = 0; |
| in_sr = FLD (in_sr); |
| out_dr = FLD (out_dr); |
| referenced |= 1 << 0; |
| referenced |= 1 << 1; |
| cycles += m32rbf_model_m32r_d_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r_d_lduh_d (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_add3.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = 0; |
| INT out_dr = 0; |
| in_sr = FLD (in_sr); |
| out_dr = FLD (out_dr); |
| referenced |= 1 << 0; |
| referenced |= 1 << 1; |
| cycles += m32rbf_model_m32r_d_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r_d_ld_plus (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_ld_plus.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = 0; |
| INT out_dr = 0; |
| in_sr = FLD (in_sr); |
| out_dr = FLD (out_dr); |
| referenced |= 1 << 0; |
| referenced |= 1 << 1; |
| cycles += m32rbf_model_m32r_d_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr); |
| } |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| INT in_dr = -1; |
| INT out_dr = -1; |
| in_dr = FLD (in_sr); |
| out_dr = FLD (out_sr); |
| referenced |= 1 << 0; |
| referenced |= 1 << 2; |
| cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 1, referenced, in_sr, in_dr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r_d_ld24 (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_ld24.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| INT in_dr = -1; |
| INT out_dr = -1; |
| out_dr = FLD (out_dr); |
| referenced |= 1 << 2; |
| cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r_d_ldi8 (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_addi.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| INT in_dr = -1; |
| INT out_dr = -1; |
| out_dr = FLD (out_dr); |
| referenced |= 1 << 2; |
| cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r_d_ldi16 (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_add3.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| INT in_dr = -1; |
| INT out_dr = -1; |
| out_dr = FLD (out_dr); |
| referenced |= 1 << 2; |
| cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r_d_lock (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_ld_plus.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = 0; |
| INT out_dr = 0; |
| in_sr = FLD (in_sr); |
| out_dr = FLD (out_dr); |
| referenced |= 1 << 0; |
| referenced |= 1 << 1; |
| cycles += m32rbf_model_m32r_d_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r_d_machi (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_st_plus.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_src1 = -1; |
| INT in_src2 = -1; |
| in_src1 = FLD (in_src1); |
| in_src2 = FLD (in_src2); |
| referenced |= 1 << 0; |
| referenced |= 1 << 1; |
| cycles += m32rbf_model_m32r_d_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r_d_maclo (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_st_plus.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_src1 = -1; |
| INT in_src2 = -1; |
| in_src1 = FLD (in_src1); |
| in_src2 = FLD (in_src2); |
| referenced |= 1 << 0; |
| referenced |= 1 << 1; |
| cycles += m32rbf_model_m32r_d_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r_d_macwhi (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_st_plus.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_src1 = -1; |
| INT in_src2 = -1; |
| in_src1 = FLD (in_src1); |
| in_src2 = FLD (in_src2); |
| referenced |= 1 << 0; |
| referenced |= 1 << 1; |
| cycles += m32rbf_model_m32r_d_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r_d_macwlo (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_st_plus.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_src1 = -1; |
| INT in_src2 = -1; |
| in_src1 = FLD (in_src1); |
| in_src2 = FLD (in_src2); |
| referenced |= 1 << 0; |
| referenced |= 1 << 1; |
| cycles += m32rbf_model_m32r_d_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r_d_mul (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_add.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| INT in_dr = -1; |
| INT out_dr = -1; |
| in_sr = FLD (in_sr); |
| in_dr = FLD (in_dr); |
| out_dr = FLD (out_dr); |
| referenced |= 1 << 0; |
| referenced |= 1 << 1; |
| referenced |= 1 << 2; |
| cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r_d_mulhi (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_st_plus.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_src1 = -1; |
| INT in_src2 = -1; |
| in_src1 = FLD (in_src1); |
| in_src2 = FLD (in_src2); |
| referenced |= 1 << 0; |
| referenced |= 1 << 1; |
| cycles += m32rbf_model_m32r_d_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r_d_mullo (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_st_plus.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_src1 = -1; |
| INT in_src2 = -1; |
| in_src1 = FLD (in_src1); |
| in_src2 = FLD (in_src2); |
| referenced |= 1 << 0; |
| referenced |= 1 << 1; |
| cycles += m32rbf_model_m32r_d_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r_d_mulwhi (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_st_plus.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_src1 = -1; |
| INT in_src2 = -1; |
| in_src1 = FLD (in_src1); |
| in_src2 = FLD (in_src2); |
| referenced |= 1 << 0; |
| referenced |= 1 << 1; |
| cycles += m32rbf_model_m32r_d_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r_d_mulwlo (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_st_plus.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_src1 = -1; |
| INT in_src2 = -1; |
| in_src1 = FLD (in_src1); |
| in_src2 = FLD (in_src2); |
| referenced |= 1 << 0; |
| referenced |= 1 << 1; |
| cycles += m32rbf_model_m32r_d_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r_d_mv (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_ld_plus.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| INT in_dr = -1; |
| INT out_dr = -1; |
| in_sr = FLD (in_sr); |
| out_dr = FLD (out_dr); |
| referenced |= 1 << 0; |
| referenced |= 1 << 2; |
| cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r_d_mvfachi (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_seth.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| INT in_dr = -1; |
| INT out_dr = -1; |
| out_dr = FLD (out_dr); |
| referenced |= 1 << 2; |
| cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r_d_mvfaclo (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_seth.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| INT in_dr = -1; |
| INT out_dr = -1; |
| out_dr = FLD (out_dr); |
| referenced |= 1 << 2; |
| cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r_d_mvfacmi (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_seth.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| INT in_dr = -1; |
| INT out_dr = -1; |
| out_dr = FLD (out_dr); |
| referenced |= 1 << 2; |
| cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r_d_mvfc (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_ld_plus.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| INT in_dr = -1; |
| INT out_dr = -1; |
| out_dr = FLD (out_dr); |
| referenced |= 1 << 2; |
| cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r_d_mvtachi (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_st_plus.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| INT in_dr = -1; |
| INT out_dr = -1; |
| in_sr = FLD (in_src1); |
| cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r_d_mvtaclo (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_st_plus.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| INT in_dr = -1; |
| INT out_dr = -1; |
| in_sr = FLD (in_src1); |
| cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r_d_mvtc (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_ld_plus.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| INT in_dr = -1; |
| INT out_dr = -1; |
| in_sr = FLD (in_sr); |
| referenced |= 1 << 0; |
| cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r_d_neg (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_ld_plus.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| INT in_dr = -1; |
| INT out_dr = -1; |
| in_sr = FLD (in_sr); |
| out_dr = FLD (out_dr); |
| referenced |= 1 << 0; |
| referenced |= 1 << 2; |
| cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r_d_nop (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_empty.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| INT in_dr = -1; |
| INT out_dr = -1; |
| cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r_d_not (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_ld_plus.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| INT in_dr = -1; |
| INT out_dr = -1; |
| in_sr = FLD (in_sr); |
| out_dr = FLD (out_dr); |
| referenced |= 1 << 0; |
| referenced |= 1 << 2; |
| cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r_d_rac (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_empty.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_src1 = -1; |
| INT in_src2 = -1; |
| cycles += m32rbf_model_m32r_d_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r_d_rach (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_empty.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_src1 = -1; |
| INT in_src2 = -1; |
| cycles += m32rbf_model_m32r_d_u_mac (current_cpu, idesc, 0, referenced, in_src1, in_src2); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r_d_rte (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_empty.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| INT in_dr = -1; |
| INT out_dr = -1; |
| cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r_d_seth (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_seth.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| INT in_dr = -1; |
| INT out_dr = -1; |
| out_dr = FLD (out_dr); |
| referenced |= 1 << 2; |
| cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r_d_sll (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_add.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| INT in_dr = -1; |
| INT out_dr = -1; |
| in_sr = FLD (in_sr); |
| in_dr = FLD (in_dr); |
| out_dr = FLD (out_dr); |
| referenced |= 1 << 0; |
| referenced |= 1 << 1; |
| referenced |= 1 << 2; |
| cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r_d_sll3 (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_add3.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| INT in_dr = -1; |
| INT out_dr = -1; |
| in_sr = FLD (in_sr); |
| out_dr = FLD (out_dr); |
| referenced |= 1 << 0; |
| referenced |= 1 << 2; |
| cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r_d_slli (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_slli.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| INT in_dr = -1; |
| INT out_dr = -1; |
| in_dr = FLD (in_dr); |
| out_dr = FLD (out_dr); |
| referenced |= 1 << 1; |
| referenced |= 1 << 2; |
| cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r_d_sra (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_add.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| INT in_dr = -1; |
| INT out_dr = -1; |
| in_sr = FLD (in_sr); |
| in_dr = FLD (in_dr); |
| out_dr = FLD (out_dr); |
| referenced |= 1 << 0; |
| referenced |= 1 << 1; |
| referenced |= 1 << 2; |
| cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r_d_sra3 (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_add3.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| INT in_dr = -1; |
| INT out_dr = -1; |
| in_sr = FLD (in_sr); |
| out_dr = FLD (out_dr); |
| referenced |= 1 << 0; |
| referenced |= 1 << 2; |
| cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r_d_srai (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_slli.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| INT in_dr = -1; |
| INT out_dr = -1; |
| in_dr = FLD (in_dr); |
| out_dr = FLD (out_dr); |
| referenced |= 1 << 1; |
| referenced |= 1 << 2; |
| cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r_d_srl (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_add.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| INT in_dr = -1; |
| INT out_dr = -1; |
| in_sr = FLD (in_sr); |
| in_dr = FLD (in_dr); |
| out_dr = FLD (out_dr); |
| referenced |= 1 << 0; |
| referenced |= 1 << 1; |
| referenced |= 1 << 2; |
| cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r_d_srl3 (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_add3.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| INT in_dr = -1; |
| INT out_dr = -1; |
| in_sr = FLD (in_sr); |
| out_dr = FLD (out_dr); |
| referenced |= 1 << 0; |
| referenced |= 1 << 2; |
| cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r_d_srli (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_slli.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| INT in_dr = -1; |
| INT out_dr = -1; |
| in_dr = FLD (in_dr); |
| out_dr = FLD (out_dr); |
| referenced |= 1 << 1; |
| referenced |= 1 << 2; |
| cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r_d_st (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_st_plus.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_src1 = 0; |
| INT in_src2 = 0; |
| in_src1 = FLD (in_src1); |
| in_src2 = FLD (in_src2); |
| referenced |= 1 << 0; |
| referenced |= 1 << 1; |
| cycles += m32rbf_model_m32r_d_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r_d_st_d (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_st_d.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_src1 = 0; |
| INT in_src2 = 0; |
| in_src1 = FLD (in_src1); |
| in_src2 = FLD (in_src2); |
| referenced |= 1 << 0; |
| referenced |= 1 << 1; |
| cycles += m32rbf_model_m32r_d_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r_d_stb (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_st_plus.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_src1 = 0; |
| INT in_src2 = 0; |
| in_src1 = FLD (in_src1); |
| in_src2 = FLD (in_src2); |
| referenced |= 1 << 0; |
| referenced |= 1 << 1; |
| cycles += m32rbf_model_m32r_d_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r_d_stb_d (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_st_d.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_src1 = 0; |
| INT in_src2 = 0; |
| in_src1 = FLD (in_src1); |
| in_src2 = FLD (in_src2); |
| referenced |= 1 << 0; |
| referenced |= 1 << 1; |
| cycles += m32rbf_model_m32r_d_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r_d_sth (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_st_plus.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_src1 = 0; |
| INT in_src2 = 0; |
| in_src1 = FLD (in_src1); |
| in_src2 = FLD (in_src2); |
| referenced |= 1 << 0; |
| referenced |= 1 << 1; |
| cycles += m32rbf_model_m32r_d_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r_d_sth_d (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_st_d.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_src1 = 0; |
| INT in_src2 = 0; |
| in_src1 = FLD (in_src1); |
| in_src2 = FLD (in_src2); |
| referenced |= 1 << 0; |
| referenced |= 1 << 1; |
| cycles += m32rbf_model_m32r_d_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r_d_st_plus (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_st_plus.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_src1 = 0; |
| INT in_src2 = 0; |
| in_src1 = FLD (in_src1); |
| in_src2 = FLD (in_src2); |
| referenced |= 1 << 0; |
| referenced |= 1 << 1; |
| cycles += m32rbf_model_m32r_d_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2); |
| } |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| INT in_dr = -1; |
| INT out_dr = -1; |
| in_dr = FLD (in_src2); |
| out_dr = FLD (out_src2); |
| cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 1, referenced, in_sr, in_dr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r_d_st_minus (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_st_plus.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_src1 = 0; |
| INT in_src2 = 0; |
| in_src1 = FLD (in_src1); |
| in_src2 = FLD (in_src2); |
| referenced |= 1 << 0; |
| referenced |= 1 << 1; |
| cycles += m32rbf_model_m32r_d_u_store (current_cpu, idesc, 0, referenced, in_src1, in_src2); |
| } |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| INT in_dr = -1; |
| INT out_dr = -1; |
| in_dr = FLD (in_src2); |
| out_dr = FLD (out_src2); |
| cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 1, referenced, in_sr, in_dr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r_d_sub (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_add.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| INT in_dr = -1; |
| INT out_dr = -1; |
| in_sr = FLD (in_sr); |
| in_dr = FLD (in_dr); |
| out_dr = FLD (out_dr); |
| referenced |= 1 << 0; |
| referenced |= 1 << 1; |
| referenced |= 1 << 2; |
| cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r_d_subv (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_add.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| INT in_dr = -1; |
| INT out_dr = -1; |
| in_sr = FLD (in_sr); |
| in_dr = FLD (in_dr); |
| out_dr = FLD (out_dr); |
| referenced |= 1 << 0; |
| referenced |= 1 << 1; |
| referenced |= 1 << 2; |
| cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r_d_subx (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_add.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| INT in_dr = -1; |
| INT out_dr = -1; |
| in_sr = FLD (in_sr); |
| in_dr = FLD (in_dr); |
| out_dr = FLD (out_dr); |
| referenced |= 1 << 0; |
| referenced |= 1 << 1; |
| referenced |= 1 << 2; |
| cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r_d_trap (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_trap.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| INT in_dr = -1; |
| INT out_dr = -1; |
| cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r_d_unlock (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_st_plus.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = 0; |
| INT out_dr = 0; |
| cycles += m32rbf_model_m32r_d_u_load (current_cpu, idesc, 0, referenced, in_sr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r_d_clrpsw (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_clrpsw.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| INT in_dr = -1; |
| INT out_dr = -1; |
| cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r_d_setpsw (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_clrpsw.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| INT in_dr = -1; |
| INT out_dr = -1; |
| cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r_d_bset (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_bset.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| INT in_dr = -1; |
| INT out_dr = -1; |
| in_sr = FLD (in_sr); |
| referenced |= 1 << 0; |
| cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r_d_bclr (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_bset.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| INT in_dr = -1; |
| INT out_dr = -1; |
| in_sr = FLD (in_sr); |
| referenced |= 1 << 0; |
| cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_m32r_d_btst (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_bset.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| INT in_sr = -1; |
| INT in_dr = -1; |
| INT out_dr = -1; |
| in_sr = FLD (in_sr); |
| referenced |= 1 << 0; |
| cycles += m32rbf_model_m32r_d_u_exec (current_cpu, idesc, 0, referenced, in_sr, in_dr, out_dr); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_test_add (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_add.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_test_add3 (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_add3.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_test_and (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_add.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_test_and3 (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_and3.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_test_or (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_add.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_test_or3 (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_and3.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_test_xor (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_add.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_test_xor3 (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_and3.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_test_addi (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_addi.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_test_addv (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_add.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_test_addv3 (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_add3.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_test_addx (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_add.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_test_bc8 (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_bl8.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_test_bc24 (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_bl24.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_test_beq (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_beq.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_test_beqz (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_beq.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_test_bgez (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_beq.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_test_bgtz (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_beq.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_test_blez (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_beq.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_test_bltz (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_beq.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_test_bnez (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_beq.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_test_bl8 (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_bl8.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_test_bl24 (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_bl24.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_test_bnc8 (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_bl8.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_test_bnc24 (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf->fields.sfmt_bl24.f |
| const ARGBUF * UNUSED abuf = SEM_ARGBUF ((SEM_ARG) sem_arg); |
| const IDESC * UNUSED idesc = abuf->idesc; |
| int cycles = 0; |
| { |
| int referenced = 0; |
| int UNUSED insn_referenced = abuf->written; |
| cycles += m32rbf_model_test_u_exec (current_cpu, idesc, 0, referenced); |
| } |
| return cycles; |
| #undef FLD |
| } |
| |
| static int |
| model_test_bne (SIM_CPU *current_cpu, void *sem_arg) |
| { |
| #define FLD(f) abuf |