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gnu / binutils-gdb / 41e27f512a5123bc28e982264b9ceb3b78e6da85 / . / gas / config / tc-i386.c
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/* i386.c -- Assemble code for the Intel 80386
Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
2000, 2001
Free Software Foundation, Inc.
This file is part of GAS, the GNU Assembler.
GAS is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
GAS is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with GAS; see the file COPYING. If not, write to the Free
Software Foundation, 59 Temple Place - Suite 330, Boston, MA
02111-1307, USA. */
/* Intel 80386 machine specific gas.
Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
x86_64 support by Jan Hubicka (jh@suse.cz)
Bugs & suggestions are completely welcome. This is free software.
Please help us make it better. */
#include <ctype.h>
#include "as.h"
#include "subsegs.h"
#include "dwarf2dbg.h"
#include "opcode/i386.h"
#ifndef REGISTER_WARNINGS
#define REGISTER_WARNINGS 1
#endif
#ifndef INFER_ADDR_PREFIX
#define INFER_ADDR_PREFIX 1
#endif
#ifndef SCALE1_WHEN_NO_INDEX
/* Specifying a scale factor besides 1 when there is no index is
futile. eg. `mov (%ebx,2),%al' does exactly the same as
`mov (%ebx),%al'. To slavishly follow what the programmer
specified, set SCALE1_WHEN_NO_INDEX to 0. */
#define SCALE1_WHEN_NO_INDEX 1
#endif
#define true 1
#define false 0
static unsigned int mode_from_disp_size PARAMS ((unsigned int));
static int fits_in_signed_byte PARAMS ((offsetT));
static int fits_in_unsigned_byte PARAMS ((offsetT));
static int fits_in_unsigned_word PARAMS ((offsetT));
static int fits_in_signed_word PARAMS ((offsetT));
static int fits_in_unsigned_long PARAMS ((offsetT));
static int fits_in_signed_long PARAMS ((offsetT));
static int smallest_imm_type PARAMS ((offsetT));
static offsetT offset_in_range PARAMS ((offsetT, int));
static int add_prefix PARAMS ((unsigned int));
static void set_code_flag PARAMS ((int));
static void set_16bit_gcc_code_flag PARAMS ((int));
static void set_intel_syntax PARAMS ((int));
static void set_cpu_arch PARAMS ((int));
#ifdef BFD_ASSEMBLER
static bfd_reloc_code_real_type reloc
PARAMS ((int, int, int, bfd_reloc_code_real_type));
#define RELOC_ENUM enum bfd_reloc_code_real
#else
#define RELOC_ENUM int
#endif
#ifndef DEFAULT_ARCH
#define DEFAULT_ARCH "i386"
#endif
static char *default_arch = DEFAULT_ARCH;
/* 'md_assemble ()' gathers together information and puts it into a
i386_insn. */
union i386_op
{
expressionS *disps;
expressionS *imms;
const reg_entry *regs;
};
struct _i386_insn
{
/* TM holds the template for the insn were currently assembling. */
template tm;
/* SUFFIX holds the instruction mnemonic suffix if given.
(e.g. 'l' for 'movl') */
char suffix;
/* OPERANDS gives the number of given operands. */
unsigned int operands;
/* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
of given register, displacement, memory operands and immediate
operands. */
unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
/* TYPES [i] is the type (see above #defines) which tells us how to
use OP[i] for the corresponding operand. */
unsigned int types[MAX_OPERANDS];
/* Displacement expression, immediate expression, or register for each
operand. */
union i386_op op[MAX_OPERANDS];
/* Flags for operands. */
unsigned int flags[MAX_OPERANDS];
#define Operand_PCrel 1
/* Relocation type for operand */
RELOC_ENUM reloc[MAX_OPERANDS];
/* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
the base index byte below. */
const reg_entry *base_reg;
const reg_entry *index_reg;
unsigned int log2_scale_factor;
/* SEG gives the seg_entries of this insn. They are zero unless
explicit segment overrides are given. */
const seg_entry *seg[2];
/* PREFIX holds all the given prefix opcodes (usually null).
PREFIXES is the number of prefix opcodes. */
unsigned int prefixes;
unsigned char prefix[MAX_PREFIXES];
/* RM and SIB are the modrm byte and the sib byte where the
addressing modes of this insn are encoded. */
modrm_byte rm;
rex_byte rex;
sib_byte sib;
};
typedef struct _i386_insn i386_insn;
/* List of chars besides those in app.c:symbol_chars that can start an
operand. Used to prevent the scrubber eating vital white-space. */
#ifdef LEX_AT
const char extra_symbol_chars[] = "*%-(@";
#else
const char extra_symbol_chars[] = "*%-(";
#endif
/* This array holds the chars that always start a comment. If the
pre-processor is disabled, these aren't very useful. */
#if defined (TE_I386AIX) || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && ! defined (TE_LINUX) && !defined(TE_FreeBSD))
/* Putting '/' here makes it impossible to use the divide operator.
However, we need it for compatibility with SVR4 systems. */
const char comment_chars[] = "#/";
#define PREFIX_SEPARATOR '\\'
#else
const char comment_chars[] = "#";
#define PREFIX_SEPARATOR '/'
#endif
/* This array holds the chars that only start a comment at the beginning of
a line. If the line seems to have the form '# 123 filename'
.line and .file directives will appear in the pre-processed output.
Note that input_file.c hand checks for '#' at the beginning of the
first line of the input file. This is because the compiler outputs
#NO_APP at the beginning of its output.
Also note that comments started like this one will always work if
'/' isn't otherwise defined. */
#if defined (TE_I386AIX) || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) && ! defined (TE_LINUX) && !defined(TE_FreeBSD))
const char line_comment_chars[] = "";
#else
const char line_comment_chars[] = "/";
#endif
const char line_separator_chars[] = ";";
/* Chars that can be used to separate mant from exp in floating point
nums. */
const char EXP_CHARS[] = "eE";
/* Chars that mean this number is a floating point constant
As in 0f12.456
or 0d1.2345e12. */
const char FLT_CHARS[] = "fFdDxX";
/* Tables for lexical analysis. */
static char mnemonic_chars[256];
static char register_chars[256];
static char operand_chars[256];
static char identifier_chars[256];
static char digit_chars[256];
/* Lexical macros. */
#define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
#define is_operand_char(x) (operand_chars[(unsigned char) x])
#define is_register_char(x) (register_chars[(unsigned char) x])
#define is_space_char(x) ((x) == ' ')
#define is_identifier_char(x) (identifier_chars[(unsigned char) x])
#define is_digit_char(x) (digit_chars[(unsigned char) x])
/* All non-digit non-letter charcters that may occur in an operand. */
static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
/* md_assemble() always leaves the strings it's passed unaltered. To
effect this we maintain a stack of saved characters that we've smashed
with '\0's (indicating end of strings for various sub-fields of the
assembler instruction). */
static char save_stack[32];
static char *save_stack_p;
#define END_STRING_AND_SAVE(s) \
do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
#define RESTORE_END_STRING(s) \
do { *(s) = *--save_stack_p; } while (0)
/* The instruction we're assembling. */
static i386_insn i;
/* Possible templates for current insn. */
static const templates *current_templates;
/* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
static expressionS disp_expressions[2], im_expressions[2];
/* Current operand we are working on. */
static int this_operand;
/* We support four different modes. FLAG_CODE variable is used to distinguish
these. */
enum flag_code {
CODE_32BIT,
CODE_16BIT,
CODE_64BIT };
#define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
static enum flag_code flag_code;
static int use_rela_relocations = 0;
/* The names used to print error messages. */
static const char *flag_code_names[] =
{
"32",
"16",
"64"
};
/* 1 for intel syntax,
0 if att syntax. */
static int intel_syntax = 0;
/* 1 if register prefix % not required. */
static int allow_naked_reg = 0;
/* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
leave, push, and pop instructions so that gcc has the same stack
frame as in 32 bit mode. */
static char stackop_size = '\0';
/* Non-zero to quieten some warnings. */
static int quiet_warnings = 0;
/* CPU name. */
static const char *cpu_arch_name = NULL;
/* CPU feature flags. */
static unsigned int cpu_arch_flags = CpuUnknownFlags|CpuNo64;
/* If set, conditional jumps are not automatically promoted to handle
larger than a byte offset. */
static unsigned int no_cond_jump_promotion = 0;
/* Interface to relax_segment.
There are 3 major relax states for 386 jump insns because the
different types of jumps add different sizes to frags when we're
figuring out what sort of jump to choose to reach a given label. */
/* Types. */
#define UNCOND_JUMP 0
#define COND_JUMP 1
#define COND_JUMP86 2
/* Sizes. */
#define CODE16 1
#define SMALL 0
#define SMALL16 (SMALL|CODE16)
#define BIG 2
#define BIG16 (BIG|CODE16)
#ifndef INLINE
#ifdef __GNUC__
#define INLINE __inline__
#else
#define INLINE
#endif
#endif
#define ENCODE_RELAX_STATE(type, size) \
((relax_substateT) (((type) << 2) | (size)))
#define TYPE_FROM_RELAX_STATE(s) \
((s) >> 2)
#define DISP_SIZE_FROM_RELAX_STATE(s) \
((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
/* This table is used by relax_frag to promote short jumps to long
ones where necessary. SMALL (short) jumps may be promoted to BIG
(32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
don't allow a short jump in a 32 bit code segment to be promoted to
a 16 bit offset jump because it's slower (requires data size
prefix), and doesn't work, unless the destination is in the bottom
64k of the code segment (The top 16 bits of eip are zeroed). */
const relax_typeS md_relax_table[] =
{
/* The fields are:
1) most positive reach of this state,
2) most negative reach of this state,
3) how many bytes this mode will have in the variable part of the frag
4) which index into the table to try if we can't fit into this one. */
/* UNCOND_JUMP states. */
{127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
{127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
/* dword jmp adds 4 bytes to frag:
0 extra opcode bytes, 4 displacement bytes. */
{0, 0, 4, 0},
/* word jmp adds 2 byte2 to frag:
0 extra opcode bytes, 2 displacement bytes. */
{0, 0, 2, 0},
/* COND_JUMP states. */
{127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
{127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
/* dword conditionals adds 5 bytes to frag:
1 extra opcode byte, 4 displacement bytes. */
{0, 0, 5, 0},
/* word conditionals add 3 bytes to frag:
1 extra opcode byte, 2 displacement bytes. */
{0, 0, 3, 0},
/* COND_JUMP86 states. */
{127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
{127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
/* dword conditionals adds 5 bytes to frag:
1 extra opcode byte, 4 displacement bytes. */
{0, 0, 5, 0},
/* word conditionals add 4 bytes to frag:
1 displacement byte and a 3 byte long branch insn. */
{0, 0, 4, 0}
};
static const arch_entry cpu_arch[] = {
{"i8086", Cpu086 },
{"i186", Cpu086|Cpu186 },
{"i286", Cpu086|Cpu186|Cpu286 },
{"i386", Cpu086|Cpu186|Cpu286|Cpu386 },
{"i486", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486 },
{"i586", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuMMX },
{"i686", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuSSE },
{"pentium", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuMMX },
{"pentiumpro",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuSSE },
{"pentium4", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX|CpuSSE|CpuSSE2 },
{"k6", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX|Cpu3dnow },
{"athlon", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuMMX|Cpu3dnow },
{"sledgehammer",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuSledgehammer|CpuMMX|Cpu3dnow|CpuSSE|CpuSSE2 },
{NULL, 0 }
};
void
i386_align_code (fragP, count)
fragS *fragP;
int count;
{
/* Various efficient no-op patterns for aligning code labels.
Note: Don't try to assemble the instructions in the comments.
0L and 0w are not legal. */
static const char f32_1[] =
{0x90}; /* nop */
static const char f32_2[] =
{0x89,0xf6}; /* movl %esi,%esi */
static const char f32_3[] =
{0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
static const char f32_4[] =
{0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
static const char f32_5[] =
{0x90, /* nop */
0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
static const char f32_6[] =
{0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
static const char f32_7[] =
{0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
static const char f32_8[] =
{0x90, /* nop */
0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
static const char f32_9[] =
{0x89,0xf6, /* movl %esi,%esi */
0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
static const char f32_10[] =
{0x8d,0x76,0x00, /* leal 0(%esi),%esi */
0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
static const char f32_11[] =
{0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
static const char f32_12[] =
{0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
static const char f32_13[] =
{0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
static const char f32_14[] =
{0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
static const char f32_15[] =
{0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
static const char f16_3[] =
{0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
static const char f16_4[] =
{0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
static const char f16_5[] =
{0x90, /* nop */
0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
static const char f16_6[] =
{0x89,0xf6, /* mov %si,%si */
0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
static const char f16_7[] =
{0x8d,0x74,0x00, /* lea 0(%si),%si */
0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
static const char f16_8[] =
{0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
static const char *const f32_patt[] = {
f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
f32_9, f32_10, f32_11, f32_12, f32_13, f32_14, f32_15
};
static const char *const f16_patt[] = {
f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8,
f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15
};
/* ??? We can't use these fillers for x86_64, since they often kills the
upper halves. Solve later. */
if (flag_code == CODE_64BIT)
count = 1;
if (count > 0 && count <= 15)
{
if (flag_code == CODE_16BIT)
{
memcpy (fragP->fr_literal + fragP->fr_fix,
f16_patt[count - 1], count);
if (count > 8)
/* Adjust jump offset. */
fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
}
else
memcpy (fragP->fr_literal + fragP->fr_fix,
f32_patt[count - 1], count);
fragP->fr_var = count;
}
}
static char *output_invalid PARAMS ((int c));
static int i386_operand PARAMS ((char *operand_string));
static int i386_intel_operand PARAMS ((char *operand_string, int got_a_float));
static const reg_entry *parse_register PARAMS ((char *reg_string,
char **end_op));
#ifndef I386COFF
static void s_bss PARAMS ((int));
#endif
symbolS *GOT_symbol; /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
static INLINE unsigned int
mode_from_disp_size (t)
unsigned int t;
{
return (t & Disp8) ? 1 : (t & (Disp16 | Disp32 | Disp32S)) ? 2 : 0;
}
static INLINE int
fits_in_signed_byte (num)
offsetT num;
{
return (num >= -128) && (num <= 127);
}
static INLINE int
fits_in_unsigned_byte (num)
offsetT num;
{
return (num & 0xff) == num;
}
static INLINE int
fits_in_unsigned_word (num)
offsetT num;
{
return (num & 0xffff) == num;
}
static INLINE int
fits_in_signed_word (num)
offsetT num;
{
return (-32768 <= num) && (num <= 32767);
}
static INLINE int
fits_in_signed_long (num)
offsetT num ATTRIBUTE_UNUSED;
{
#ifndef BFD64
return 1;
#else
return (!(((offsetT) -1 << 31) & num)
|| (((offsetT) -1 << 31) & num) == ((offsetT) -1 << 31));
#endif
} /* fits_in_signed_long() */
static INLINE int
fits_in_unsigned_long (num)
offsetT num ATTRIBUTE_UNUSED;
{
#ifndef BFD64
return 1;
#else
return (num & (((offsetT) 2 << 31) - 1)) == num;
#endif
} /* fits_in_unsigned_long() */
static int
smallest_imm_type (num)
offsetT num;
{
if (cpu_arch_flags != (Cpu086 | Cpu186 | Cpu286 | Cpu386 | Cpu486 | CpuNo64)
&& !(cpu_arch_flags & (CpuUnknown)))
{
/* This code is disabled on the 486 because all the Imm1 forms
in the opcode table are slower on the i486. They're the
versions with the implicitly specified single-position
displacement, which has another syntax if you really want to
use that form. */
if (num == 1)
return Imm1 | Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64;
}
return (fits_in_signed_byte (num)
? (Imm8S | Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
: fits_in_unsigned_byte (num)
? (Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
: (fits_in_signed_word (num) || fits_in_unsigned_word (num))
? (Imm16 | Imm32 | Imm32S | Imm64)
: fits_in_signed_long (num)
? (Imm32 | Imm32S | Imm64)
: fits_in_unsigned_long (num)
? (Imm32 | Imm64)
: Imm64);
}
static offsetT
offset_in_range (val, size)
offsetT val;
int size;
{
addressT mask;
switch (size)
{
case 1: mask = ((addressT) 1 << 8) - 1; break;
case 2: mask = ((addressT) 1 << 16) - 1; break;
case 4: mask = ((addressT) 2 << 31) - 1; break;
#ifdef BFD64
case 8: mask = ((addressT) 2 << 63) - 1; break;
#endif
default: abort ();
}
/* If BFD64, sign extend val. */
if (!use_rela_relocations)
if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
{
char buf1[40], buf2[40];
sprint_value (buf1, val);
sprint_value (buf2, val & mask);
as_warn (_("%s shortened to %s"), buf1, buf2);
}
return val & mask;
}
/* Returns 0 if attempting to add a prefix where one from the same
class already exists, 1 if non rep/repne added, 2 if rep/repne
added. */
static int
add_prefix (prefix)
unsigned int prefix;
{
int ret = 1;
int q;
if (prefix >= 0x40 && prefix < 0x50 && flag_code == CODE_64BIT)
q = REX_PREFIX;
else
switch (prefix)
{
default:
abort ();
case CS_PREFIX_OPCODE:
case DS_PREFIX_OPCODE:
case ES_PREFIX_OPCODE:
case FS_PREFIX_OPCODE:
case GS_PREFIX_OPCODE:
case SS_PREFIX_OPCODE:
q = SEG_PREFIX;
break;
case REPNE_PREFIX_OPCODE:
case REPE_PREFIX_OPCODE:
ret = 2;
/* fall thru */
case LOCK_PREFIX_OPCODE:
q = LOCKREP_PREFIX;
break;
case FWAIT_OPCODE:
q = WAIT_PREFIX;
break;
case ADDR_PREFIX_OPCODE:
q = ADDR_PREFIX;
break;
case DATA_PREFIX_OPCODE:
q = DATA_PREFIX;
break;
}
if (i.prefix[q])
{
as_bad (_("same type of prefix used twice"));
return 0;
}
i.prefixes += 1;
i.prefix[q] = prefix;
return ret;
}
static void
set_code_flag (value)
int value;
{
flag_code = value;
cpu_arch_flags &= ~(Cpu64 | CpuNo64);
cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
if (value == CODE_64BIT && !(cpu_arch_flags & CpuSledgehammer))
{
as_bad (_("64bit mode not supported on this CPU."));
}
if (value == CODE_32BIT && !(cpu_arch_flags & Cpu386))
{
as_bad (_("32bit mode not supported on this CPU."));
}
stackop_size = '\0';
}
static void
set_16bit_gcc_code_flag (new_code_flag)
int new_code_flag;
{
flag_code = new_code_flag;
cpu_arch_flags &= ~(Cpu64 | CpuNo64);
cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
stackop_size = 'l';
}
static void
set_intel_syntax (syntax_flag)
int syntax_flag;
{
/* Find out if register prefixing is specified. */
int ask_naked_reg = 0;
SKIP_WHITESPACE ();
if (! is_end_of_line[(unsigned char) *input_line_pointer])
{
char *string = input_line_pointer;
int e = get_symbol_end ();
if (strcmp (string, "prefix") == 0)
ask_naked_reg = 1;
else if (strcmp (string, "noprefix") == 0)
ask_naked_reg = -1;
else
as_bad (_("bad argument to syntax directive."));
*input_line_pointer = e;
}
demand_empty_rest_of_line ();
intel_syntax = syntax_flag;
if (ask_naked_reg == 0)
{
#ifdef BFD_ASSEMBLER
allow_naked_reg = (intel_syntax
&& (bfd_get_symbol_leading_char (stdoutput) != '\0'));
#else
/* Conservative default. */
allow_naked_reg = 0;
#endif
}
else
allow_naked_reg = (ask_naked_reg < 0);
}
static void
set_cpu_arch (dummy)
int dummy ATTRIBUTE_UNUSED;
{
SKIP_WHITESPACE ();
if (! is_end_of_line[(unsigned char) *input_line_pointer])
{
char *string = input_line_pointer;
int e = get_symbol_end ();
int i;
for (i = 0; cpu_arch[i].name; i++)
{
if (strcmp (string, cpu_arch[i].name) == 0)
{
cpu_arch_name = cpu_arch[i].name;
cpu_arch_flags = (cpu_arch[i].flags
| (flag_code == CODE_64BIT ? Cpu64 : CpuNo64));
break;
}
}
if (!cpu_arch[i].name)
as_bad (_("no such architecture: `%s'"), string);
*input_line_pointer = e;
}
else
as_bad (_("missing cpu architecture"));
no_cond_jump_promotion = 0;
if (*input_line_pointer == ','
&& ! is_end_of_line[(unsigned char) input_line_pointer[1]])
{
char *string = ++input_line_pointer;
int e = get_symbol_end ();
if (strcmp (string, "nojumps") == 0)
no_cond_jump_promotion = 1;
else if (strcmp (string, "jumps") == 0)
;
else
as_bad (_("no such architecture modifier: `%s'"), string);
*input_line_pointer = e;
}
demand_empty_rest_of_line ();
}
const pseudo_typeS md_pseudo_table[] =
{
#if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
{"align", s_align_bytes, 0},
#else
{"align", s_align_ptwo, 0},
#endif
{"arch", set_cpu_arch, 0},
#ifndef I386COFF
{"bss", s_bss, 0},
#endif
{"ffloat", float_cons, 'f'},
{"dfloat", float_cons, 'd'},
{"tfloat", float_cons, 'x'},
{"value", cons, 2},
{"noopt", s_ignore, 0},
{"optim", s_ignore, 0},
{"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
{"code16", set_code_flag, CODE_16BIT},
{"code32", set_code_flag, CODE_32BIT},
{"code64", set_code_flag, CODE_64BIT},
{"intel_syntax", set_intel_syntax, 1},
{"att_syntax", set_intel_syntax, 0},
{"file", dwarf2_directive_file, 0},
{"loc", dwarf2_directive_loc, 0},
{0, 0, 0}
};
/* For interface with expression (). */
extern char *input_line_pointer;
/* Hash table for instruction mnemonic lookup. */
static struct hash_control *op_hash;
/* Hash table for register lookup. */
static struct hash_control *reg_hash;
#ifdef BFD_ASSEMBLER
unsigned long
i386_mach ()
{
if (!strcmp (default_arch, "x86_64"))
return bfd_mach_x86_64;
else if (!strcmp (default_arch, "i386"))
return bfd_mach_i386_i386;
else
as_fatal (_("Unknown architecture"));
}
#endif
void
md_begin ()
{
const char *hash_err;
/* Initialize op_hash hash table. */
op_hash = hash_new ();
{
register const template *optab;
register templates *core_optab;
/* Setup for loop. */
optab = i386_optab;
core_optab = (templates *) xmalloc (sizeof (templates));
core_optab->start = optab;
while (1)
{
++optab;
if (optab->name == NULL
|| strcmp (optab->name, (optab - 1)->name) != 0)
{
/* different name --> ship out current template list;
add to hash table; & begin anew. */
core_optab->end = optab;
hash_err = hash_insert (op_hash,
(optab - 1)->name,
(PTR) core_optab);
if (hash_err)
{
as_fatal (_("Internal Error: Can't hash %s: %s"),
(optab - 1)->name,
hash_err);
}
if (optab->name == NULL)
break;
core_optab = (templates *) xmalloc (sizeof (templates));
core_optab->start = optab;
}
}
}
/* Initialize reg_hash hash table. */
reg_hash = hash_new ();
{
register const reg_entry *regtab;
for (regtab = i386_regtab;
regtab < i386_regtab + sizeof (i386_regtab) / sizeof (i386_regtab[0]);
regtab++)
{
hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
if (hash_err)
as_fatal (_("Internal Error: Can't hash %s: %s"),
regtab->reg_name,
hash_err);
}
}
/* Fill in lexical tables: mnemonic_chars, operand_chars. */
{
register int c;
register char *p;
for (c = 0; c < 256; c++)
{
if (isdigit (c))
{
digit_chars[c] = c;
mnemonic_chars[c] = c;
register_chars[c] = c;
operand_chars[c] = c;
}
else if (islower (c))
{
mnemonic_chars[c] = c;
register_chars[c] = c;
operand_chars[c] = c;
}
else if (isupper (c))
{
mnemonic_chars[c] = tolower (c);
register_chars[c] = mnemonic_chars[c];
operand_chars[c] = c;
}
if (isalpha (c) || isdigit (c))
identifier_chars[c] = c;
else if (c >= 128)
{
identifier_chars[c] = c;
operand_chars[c] = c;
}
}
#ifdef LEX_AT
identifier_chars['@'] = '@';
#endif
digit_chars['-'] = '-';
identifier_chars['_'] = '_';
identifier_chars['.'] = '.';
for (p = operand_special_chars; *p != '\0'; p++)
operand_chars[(unsigned char) *p] = *p;
}
#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
{
record_alignment (text_section, 2);
record_alignment (data_section, 2);
record_alignment (bss_section, 2);
}
#endif
}
void
i386_print_statistics (file)
FILE *file;
{
hash_print_statistics (file, "i386 opcode", op_hash);
hash_print_statistics (file, "i386 register", reg_hash);
}
#ifdef DEBUG386
/* Debugging routines for md_assemble. */
static void pi PARAMS ((char *, i386_insn *));
static void pte PARAMS ((template *));
static void pt PARAMS ((unsigned int));
static void pe PARAMS ((expressionS *));
static void ps PARAMS ((symbolS *));
static void
pi (line, x)
char *line;
i386_insn *x;
{
unsigned int i;
fprintf (stdout, "%s: template ", line);
pte (&x->tm);
fprintf (stdout, " address: base %s index %s scale %x\n",
x->base_reg ? x->base_reg->reg_name : "none",
x->index_reg ? x->index_reg->reg_name : "none",
x->log2_scale_factor);
fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
x->rm.mode, x->rm.reg, x->rm.regmem);
fprintf (stdout, " sib: base %x index %x scale %x\n",
x->sib.base, x->sib.index, x->sib.scale);
fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
x->rex.mode64, x->rex.extX, x->rex.extY, x->rex.extZ);
for (i = 0; i < x->operands; i++)
{
fprintf (stdout, " #%d: ", i + 1);
pt (x->types[i]);
fprintf (stdout, "\n");
if (x->types[i]
& (Reg | SReg2 | SReg3 | Control | Debug | Test | RegMMX | RegXMM))
fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
if (x->types[i] & Imm)
pe (x->op[i].imms);
if (x->types[i] & Disp)
pe (x->op[i].disps);
}
}
static void
pte (t)
template *t;
{
unsigned int i;
fprintf (stdout, " %d operands ", t->operands);
fprintf (stdout, "opcode %x ", t->base_opcode);
if (t->extension_opcode != None)
fprintf (stdout, "ext %x ", t->extension_opcode);
if (t->opcode_modifier & D)
fprintf (stdout, "D");
if (t->opcode_modifier & W)
fprintf (stdout, "W");
fprintf (stdout, "\n");
for (i = 0; i < t->operands; i++)
{
fprintf (stdout, " #%d type ", i + 1);
pt (t->operand_types[i]);
fprintf (stdout, "\n");
}
}
static void
pe (e)
expressionS *e;
{
fprintf (stdout, " operation %d\n", e->X_op);
fprintf (stdout, " add_number %ld (%lx)\n",
(long) e->X_add_number, (long) e->X_add_number);
if (e->X_add_symbol)
{
fprintf (stdout, " add_symbol ");
ps (e->X_add_symbol);
fprintf (stdout, "\n");
}
if (e->X_op_symbol)
{
fprintf (stdout, " op_symbol ");
ps (e->X_op_symbol);
fprintf (stdout, "\n");
}
}
static void
ps (s)
symbolS *s;
{
fprintf (stdout, "%s type %s%s",
S_GET_NAME (s),
S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
segment_name (S_GET_SEGMENT (s)));
}
struct type_name
{
unsigned int mask;
char *tname;
}
type_names[] =
{
{ Reg8, "r8" },
{ Reg16, "r16" },
{ Reg32, "r32" },
{ Reg64, "r64" },
{ Imm8, "i8" },
{ Imm8S, "i8s" },
{ Imm16, "i16" },
{ Imm32, "i32" },
{ Imm32S, "i32s" },
{ Imm64, "i64" },
{ Imm1, "i1" },
{ BaseIndex, "BaseIndex" },
{ Disp8, "d8" },
{ Disp16, "d16" },
{ Disp32, "d32" },
{ Disp32S, "d32s" },
{ Disp64, "d64" },
{ InOutPortReg, "InOutPortReg" },
{ ShiftCount, "ShiftCount" },
{ Control, "control reg" },
{ Test, "test reg" },
{ Debug, "debug reg" },
{ FloatReg, "FReg" },
{ FloatAcc, "FAcc" },
{ SReg2, "SReg2" },
{ SReg3, "SReg3" },
{ Acc, "Acc" },
{ JumpAbsolute, "Jump Absolute" },
{ RegMMX, "rMMX" },
{ RegXMM, "rXMM" },
{ EsSeg, "es" },
{ 0, "" }
};
static void
pt (t)
unsigned int t;
{
register struct type_name *ty;
for (ty = type_names; ty->mask; ty++)
if (t & ty->mask)
fprintf (stdout, "%s, ", ty->tname);
fflush (stdout);
}
#endif /* DEBUG386 */
int
tc_i386_force_relocation (fixp)
struct fix *fixp;
{
#ifdef BFD_ASSEMBLER
if (fixp->fx_r_type == BFD_RELOC_VTABLE_INHERIT
|| fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
return 1;
return 0;
#else
/* For COFF. */
return fixp->fx_r_type == 7;
#endif
}
#ifdef BFD_ASSEMBLER
static bfd_reloc_code_real_type
reloc (size, pcrel, sign, other)
int size;
int pcrel;
int sign;
bfd_reloc_code_real_type other;
{
if (other != NO_RELOC)
return other;
if (pcrel)
{
if (!sign)
as_bad (_("There are no unsigned pc-relative relocations"));
switch (size)
{
case 1: return BFD_RELOC_8_PCREL;
case 2: return BFD_RELOC_16_PCREL;
case 4: return BFD_RELOC_32_PCREL;
}
as_bad (_("can not do %d byte pc-relative relocation"), size);
}
else
{
if (sign)
switch (size)
{
case 4: return BFD_RELOC_X86_64_32S;
}
else
switch (size)
{
case 1: return BFD_RELOC_8;
case 2: return BFD_RELOC_16;
case 4: return BFD_RELOC_32;
case 8: return BFD_RELOC_64;
}
as_bad (_("can not do %s %d byte relocation"),
sign ? "signed" : "unsigned", size);
}
abort ();
return BFD_RELOC_NONE;
}
/* Here we decide which fixups can be adjusted to make them relative to
the beginning of the section instead of the symbol. Basically we need
to make sure that the dynamic relocations are done correctly, so in
some cases we force the original symbol to be used. */
int
tc_i386_fix_adjustable (fixP)
fixS *fixP;
{
#if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
/* Prevent all adjustments to global symbols, or else dynamic
linking will not work correctly. */
if (S_IS_EXTERNAL (fixP->fx_addsy)
|| S_IS_WEAK (fixP->fx_addsy))
return 0;
#endif
/* adjust_reloc_syms doesn't know about the GOT. */
if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
|| fixP->fx_r_type == BFD_RELOC_386_PLT32
|| fixP->fx_r_type == BFD_RELOC_386_GOT32
|| fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
|| fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
|| fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
|| fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
|| fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
return 0;
return 1;
}
#else
#define reloc(SIZE,PCREL,SIGN,OTHER) 0
#define BFD_RELOC_16 0
#define BFD_RELOC_32 0
#define BFD_RELOC_16_PCREL 0
#define BFD_RELOC_32_PCREL 0
#define BFD_RELOC_386_PLT32 0
#define BFD_RELOC_386_GOT32 0
#define BFD_RELOC_386_GOTOFF 0
#define BFD_RELOC_X86_64_PLT32 0
#define BFD_RELOC_X86_64_GOT32 0
#define BFD_RELOC_X86_64_GOTPCREL 0
#endif
static int intel_float_operand PARAMS ((char *mnemonic));
static int
intel_float_operand (mnemonic)
char *mnemonic;
{
if (mnemonic[0] == 'f' && mnemonic[1] == 'i')
return 2;
if (mnemonic[0] == 'f')
return 1;
return 0;
}
/* This is the guts of the machine-dependent assembler. LINE points to a
machine dependent instruction. This function is supposed to emit
the frags/bytes it assembles to. */
void
md_assemble (line)
char *line;
{
/* Points to template once we've found it. */
const template *t;
int j;
char mnemonic[MAX_MNEM_SIZE];
/* Initialize globals. */
memset (&i, '\0', sizeof (i));
for (j = 0; j < MAX_OPERANDS; j++)
i.reloc[j] = NO_RELOC;
memset (disp_expressions, '\0', sizeof (disp_expressions));
memset (im_expressions, '\0', sizeof (im_expressions));
save_stack_p = save_stack;
/* First parse an instruction mnemonic & call i386_operand for the operands.
We assume that the scrubber has arranged it so that line[0] is the valid
start of a (possibly prefixed) mnemonic. */
{
char *l = line;
char *token_start = l;
char *mnem_p;
/* Non-zero if we found a prefix only acceptable with string insns. */
const char *expecting_string_instruction = NULL;
while (1)
{
mnem_p = mnemonic;
while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
{
mnem_p++;
if (mnem_p >= mnemonic + sizeof (mnemonic))
{
as_bad (_("no such instruction: `%s'"), token_start);
return;
}
l++;
}
if (!is_space_char (*l)
&& *l != END_OF_INSN
&& *l != PREFIX_SEPARATOR)
{
as_bad (_("invalid character %s in mnemonic"),
output_invalid (*l));
return;
}
if (token_start == l)
{
if (*l == PREFIX_SEPARATOR)
as_bad (_("expecting prefix; got nothing"));
else
as_bad (_("expecting mnemonic; got nothing"));
return;
}
/* Look up instruction (or prefix) via hash table. */
current_templates = hash_find (op_hash, mnemonic);
if (*l != END_OF_INSN
&& (! is_space_char (*l) || l[1] != END_OF_INSN)
&& current_templates
&& (current_templates->start->opcode_modifier & IsPrefix))
{
/* If we are in 16-bit mode, do not allow addr16 or data16.
Similarly, in 32-bit mode, do not allow addr32 or data32. */
if ((current_templates->start->opcode_modifier & (Size16 | Size32))
&& (((current_templates->start->opcode_modifier & Size32) != 0)
^ (flag_code == CODE_16BIT)))
{
as_bad (_("redundant %s prefix"),
current_templates->start->name);
return;
}
/* Add prefix, checking for repeated prefixes. */
switch (add_prefix (current_templates->start->base_opcode))
{
case 0:
return;
case 2:
expecting_string_instruction = current_templates->start->name;
break;
}
/* Skip past PREFIX_SEPARATOR and reset token_start. */
token_start = ++l;
}
else
break;
}
if (!current_templates)
{
/* See if we can get a match by trimming off a suffix. */
switch (mnem_p[-1])
{
case WORD_MNEM_SUFFIX:
case BYTE_MNEM_SUFFIX:
case QWORD_MNEM_SUFFIX:
i.suffix = mnem_p[-1];
mnem_p[-1] = '\0';
current_templates = hash_find (op_hash, mnemonic);
break;
case SHORT_MNEM_SUFFIX:
case LONG_MNEM_SUFFIX:
if (!intel_syntax)
{
i.suffix = mnem_p[-1];
mnem_p[-1] = '\0';
current_templates = hash_find (op_hash, mnemonic);
}
break;
/* Intel Syntax. */
case 'd':
if (intel_syntax)
{
if (intel_float_operand (mnemonic))
i.suffix = SHORT_MNEM_SUFFIX;
else
i.suffix = LONG_MNEM_SUFFIX;
mnem_p[-1] = '\0';
current_templates = hash_find (op_hash, mnemonic);
}
break;
}
if (!current_templates)
{
as_bad (_("no such instruction: `%s'"), token_start);
return;
}
}
/* Check if instruction is supported on specified architecture. */
if (cpu_arch_flags != 0)
{
if ((current_templates->start->cpu_flags & ~(Cpu64 | CpuNo64))
& ~(cpu_arch_flags & ~(Cpu64 | CpuNo64)))
{
as_warn (_("`%s' is not supported on `%s'"),
current_templates->start->name, cpu_arch_name);
}
else if ((Cpu386 & ~cpu_arch_flags) && (flag_code != CODE_16BIT))
{
as_warn (_("use .code16 to ensure correct addressing mode"));
}
}
/* Check for rep/repne without a string instruction. */
if (expecting_string_instruction
&& !(current_templates->start->opcode_modifier & IsString))
{
as_bad (_("expecting string instruction after `%s'"),
expecting_string_instruction);
return;
}
/* There may be operands to parse. */
if (*l != END_OF_INSN)
{
/* 1 if operand is pending after ','. */
unsigned int expecting_operand = 0;
/* Non-zero if operand parens not balanced. */
unsigned int paren_not_balanced;
do
{
/* Skip optional white space before operand. */
if (is_space_char (*l))
++l;
if (!is_operand_char (*l) && *l != END_OF_INSN)
{
as_bad (_("invalid character %s before operand %d"),
output_invalid (*l),
i.operands + 1);
return;
}
token_start = l; /* after white space */
paren_not_balanced = 0;
while (paren_not_balanced || *l != ',')
{
if (*l == END_OF_INSN)
{
if (paren_not_balanced)
{
if (!intel_syntax)
as_bad (_("unbalanced parenthesis in operand %d."),
i.operands + 1);
else
as_bad (_("unbalanced brackets in operand %d."),
i.operands + 1);
return;
}
else
break; /* we are done */
}
else if (!is_operand_char (*l) && !is_space_char (*l))
{
as_bad (_("invalid character %s in operand %d"),
output_invalid (*l),
i.operands + 1);
return;
}
if (!intel_syntax)
{
if (*l == '(')
++paren_not_balanced;
if (*l == ')')
--paren_not_balanced;
}
else
{
if (*l == '[')
++paren_not_balanced;
if (*l == ']')
--paren_not_balanced;
}
l++;
}
if (l != token_start)
{ /* Yes, we've read in another operand. */
unsigned int operand_ok;
this_operand = i.operands++;
if (i.operands > MAX_OPERANDS)
{
as_bad (_("spurious operands; (%d operands/instruction max)"),
MAX_OPERANDS);
return;
}
/* Now parse operand adding info to 'i' as we go along. */
END_STRING_AND_SAVE (l);
if (intel_syntax)
operand_ok =
i386_intel_operand (token_start,
intel_float_operand (mnemonic));
else
operand_ok = i386_operand (token_start);
RESTORE_END_STRING (l);
if (!operand_ok)
return;
}
else
{
if (expecting_operand)
{
expecting_operand_after_comma:
as_bad (_("expecting operand after ','; got nothing"));
return;
}
if (*l == ',')
{
as_bad (_("expecting operand before ','; got nothing"));
return;
}
}
/* Now *l must be either ',' or END_OF_INSN. */
if (*l == ',')
{
if (*++l == END_OF_INSN)
{
/* Just skip it, if it's \n complain. */
goto expecting_operand_after_comma;
}
expecting_operand = 1;
}
}
while (*l != END_OF_INSN);
}
}
/* Now we've parsed the mnemonic into a set of templates, and have the
operands at hand.
Next, we find a template that matches the given insn,
making sure the overlap of the given operands types is consistent
with the template operand types. */
#define MATCH(overlap, given, template) \
((overlap & ~JumpAbsolute) \
&& ((given) & (BaseIndex|JumpAbsolute)) == ((overlap) & (BaseIndex|JumpAbsolute)))
/* If given types r0 and r1 are registers they must be of the same type
unless the expected operand type register overlap is null.
Note that Acc in a template matches every size of reg. */
#define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
( ((g0) & Reg) == 0 || ((g1) & Reg) == 0 || \
((g0) & Reg) == ((g1) & Reg) || \
((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
{
register unsigned int overlap0, overlap1;
unsigned int overlap2;
unsigned int found_reverse_match;
int suffix_check;
/* All intel opcodes have reversed operands except for "bound" and
"enter". We also don't reverse intersegment "jmp" and "call"
instructions with 2 immediate operands so that the immediate segment
precedes the offset, as it does when in AT&T mode. "enter" and the
intersegment "jmp" and "call" instructions are the only ones that
have two immediate operands. */
if (intel_syntax && i.operands > 1
&& (strcmp (mnemonic, "bound") != 0)
&& !((i.types[0] & Imm) && (i.types[1] & Imm)))
{
union i386_op temp_op;
unsigned int temp_type;
RELOC_ENUM temp_reloc;
int xchg1 = 0;
int xchg2 = 0;
if (i.operands == 2)
{
xchg1 = 0;
xchg2 = 1;
}
else if (i.operands == 3)
{
xchg1 = 0;
xchg2 = 2;
}
temp_type = i.types[xchg2];
i.types[xchg2] = i.types[xchg1];
i.types[xchg1] = temp_type;
temp_op = i.op[xchg2];
i.op[xchg2] = i.op[xchg1];
i.op[xchg1] = temp_op;
temp_reloc = i.reloc[xchg2];
i.reloc[xchg2] = i.reloc[xchg1];
i.reloc[xchg1] = temp_reloc;
if (i.mem_operands == 2)
{
const seg_entry *temp_seg;
temp_seg = i.seg[0];
i.seg[0] = i.seg[1];
i.seg[1] = temp_seg;
}
}
if (i.imm_operands)
{
/* Try to ensure constant immediates are represented in the smallest
opcode possible. */
char guess_suffix = 0;
int op;
if (i.suffix)
guess_suffix = i.suffix;
else if (i.reg_operands)
{
/* Figure out a suffix from the last register operand specified.
We can't do this properly yet, ie. excluding InOutPortReg,
but the following works for instructions with immediates.
In any case, we can't set i.suffix yet. */
for (op = i.operands; --op >= 0;)
if (i.types[op] & Reg)
{
if (i.types[op] & Reg8)
guess_suffix = BYTE_MNEM_SUFFIX;
else if (i.types[op] & Reg16)
guess_suffix = WORD_MNEM_SUFFIX;
else if (i.types[op] & Reg32)
guess_suffix = LONG_MNEM_SUFFIX;
else if (i.types[op] & Reg64)
guess_suffix = QWORD_MNEM_SUFFIX;
break;
}
}
else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
guess_suffix = WORD_MNEM_SUFFIX;
for (op = i.operands; --op >= 0;)
if (i.types[op] & Imm)
{
switch (i.op[op].imms->X_op)
{
case O_constant:
/* If a suffix is given, this operand may be shortened. */
switch (guess_suffix)
{
case LONG_MNEM_SUFFIX:
i.types[op] |= Imm32 | Imm64;
break;
case WORD_MNEM_SUFFIX:
i.types[op] |= Imm16 | Imm32S | Imm32 | Imm64;
break;
case BYTE_MNEM_SUFFIX:
i.types[op] |= Imm16 | Imm8 | Imm8S | Imm32S | Imm32 | Imm64;
break;
}
/* If this operand is at most 16 bits, convert it
to a signed 16 bit number before trying to see
whether it will fit in an even smaller size.
This allows a 16-bit operand such as $0xffe0 to
be recognised as within Imm8S range. */
if ((i.types[op] & Imm16)
&& (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
{
i.op[op].imms->X_add_number =
(((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
}
if ((i.types[op] & Imm32)
&& (i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1)) == 0)
{
i.op[op].imms->X_add_number =
(i.op[op].imms->X_add_number ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
}
i.types[op] |= smallest_imm_type (i.op[op].imms->X_add_number);
/* We must avoid matching of Imm32 templates when 64bit only immediate is available. */
if (guess_suffix == QWORD_MNEM_SUFFIX)
i.types[op] &= ~Imm32;
break;
case O_absent:
case O_register:
abort ();
/* Symbols and expressions. */
default:
/* Convert symbolic operand to proper sizes for matching. */
switch (guess_suffix)
{
case QWORD_MNEM_SUFFIX:
i.types[op] = Imm64 | Imm32S;
break;
case LONG_MNEM_SUFFIX:
i.types[op] = Imm32 | Imm64;
break;
case WORD_MNEM_SUFFIX:
i.types[op] = Imm16 | Imm32 | Imm64;
break;
break;
case BYTE_MNEM_SUFFIX:
i.types[op] = Imm8 | Imm8S | Imm16 | Imm32S | Imm32;
break;
break;
}
break;
}
}
}
if (i.disp_operands)
{
/* Try to use the smallest displacement type too. */
int op;
for (op = i.operands; --op >= 0;)
if ((i.types[op] & Disp)
&& i.op[op].disps->X_op == O_constant)
{
offsetT disp = i.op[op].disps->X_add_number;
if (i.types[op] & Disp16)
{
/* We know this operand is at most 16 bits, so
convert to a signed 16 bit number before trying
to see whether it will fit in an even smaller
size. */
disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
}
else if (i.types[op] & Disp32)
{
/* We know this operand is at most 32 bits, so convert to a
signed 32 bit number before trying to see whether it will
fit in an even smaller size. */
disp &= (((offsetT) 2 << 31) - 1);
disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
}
if (flag_code == CODE_64BIT)
{
if (fits_in_signed_long (disp))
i.types[op] |= Disp32S;
if (fits_in_unsigned_long (disp))
i.types[op] |= Disp32;
}
if ((i.types[op] & (Disp32 | Disp32S | Disp16))
&& fits_in_signed_byte (disp))
i.types[op] |= Disp8;
}
}
overlap0 = 0;
overlap1 = 0;
overlap2 = 0;
found_reverse_match = 0;
suffix_check = (i.suffix == BYTE_MNEM_SUFFIX
? No_bSuf
: (i.suffix == WORD_MNEM_SUFFIX
? No_wSuf
: (i.suffix == SHORT_MNEM_SUFFIX
? No_sSuf
: (i.suffix == LONG_MNEM_SUFFIX
? No_lSuf
: (i.suffix == QWORD_MNEM_SUFFIX
? No_qSuf
: (i.suffix == LONG_DOUBLE_MNEM_SUFFIX ? No_xSuf : 0))))));
for (t = current_templates->start;
t < current_templates->end;
t++)
{
/* Must have right number of operands. */
if (i.operands != t->operands)
continue;
/* Check the suffix, except for some instructions in intel mode. */
if ((t->opcode_modifier & suffix_check)
&& !(intel_syntax
&& (t->opcode_modifier & IgnoreSize))
&& !(intel_syntax
&& t->base_opcode == 0xd9
&& (t->extension_opcode == 5 /* 0xd9,5 "fldcw" */
|| t->extension_opcode == 7))) /* 0xd9,7 "f{n}stcw" */
continue;
/* Do not verify operands when there are none. */
else if (!t->operands)
{
if (t->cpu_flags & ~cpu_arch_flags)
continue;
/* We've found a match; break out of loop. */
break;
}
overlap0 = i.types[0] & t->operand_types[0];
switch (t->operands)
{
case 1:
if (!MATCH (overlap0, i.types[0], t->operand_types[0]))
continue;
break;
case 2:
case 3:
overlap1 = i.types[1] & t->operand_types[1];
if (!MATCH (overlap0, i.types[0], t->operand_types[0])
|| !MATCH (overlap1, i.types[1], t->operand_types[1])
|| !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
t->operand_types[0],
overlap1, i.types[1],
t->operand_types[1]))
{
/* Check if other direction is valid ... */
if ((t->opcode_modifier & (D|FloatD)) == 0)
continue;
/* Try reversing direction of operands. */
overlap0 = i.types[0] & t->operand_types[1];
overlap1 = i.types[1] & t->operand_types[0];
if (!MATCH (overlap0, i.types[0], t->operand_types[1])
|| !MATCH (overlap1, i.types[1], t->operand_types[0])
|| !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
t->operand_types[1],
overlap1, i.types[1],
t->operand_types[0]))
{
/* Does not match either direction. */
continue;
}
/* found_reverse_match holds which of D or FloatDR
we've found. */
found_reverse_match = t->opcode_modifier & (D|FloatDR);
}
/* Found a forward 2 operand match here. */
else if (t->operands == 3)
{
/* Here we make use of the fact that there are no
reverse match 3 operand instructions, and all 3
operand instructions only need to be checked for
register consistency between operands 2 and 3. */
overlap2 = i.types[2] & t->operand_types[2];
if (!MATCH (overlap2, i.types[2], t->operand_types[2])
|| !CONSISTENT_REGISTER_MATCH (overlap1, i.types[1],
t->operand_types[1],
overlap2, i.types[2],
t->operand_types[2]))
continue;
}
/* Found either forward/reverse 2 or 3 operand match here:
slip through to break. */
}
if (t->cpu_flags & ~cpu_arch_flags)
{
found_reverse_match = 0;
continue;
}
/* We've found a match; break out of loop. */
break;
}
if (t == current_templates->end)
{
/* We found no match. */
as_bad (_("suffix or operands invalid for `%s'"),
current_templates->start->name);
return;
}
if (!quiet_warnings)
{
if (!intel_syntax
&& ((i.types[0] & JumpAbsolute)
!= (t->operand_types[0] & JumpAbsolute)))
{
as_warn (_("indirect %s without `*'"), t->name);
}
if ((t->opcode_modifier & (IsPrefix|IgnoreSize))
== (IsPrefix|IgnoreSize))
{
/* Warn them that a data or address size prefix doesn't
affect assembly of the next line of code. */
as_warn (_("stand-alone `%s' prefix"), t->name);
}
}
/* Copy the template we found. */
i.tm = *t;
if (found_reverse_match)
{
/* If we found a reverse match we must alter the opcode
direction bit. found_reverse_match holds bits to change
(different for int & float insns). */
i.tm.base_opcode ^= found_reverse_match;
i.tm.operand_types[0] = t->operand_types[1];
i.tm.operand_types[1] = t->operand_types[0];
}
/* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
if (SYSV386_COMPAT
&& intel_syntax
&& (i.tm.base_opcode & 0xfffffde0) == 0xdce0)
i.tm.base_opcode ^= FloatR;
if (i.tm.opcode_modifier & FWait)
if (! add_prefix (FWAIT_OPCODE))
return;
/* Check string instruction segment overrides. */
if ((i.tm.opcode_modifier & IsString) != 0 && i.mem_operands != 0)
{
int mem_op = (i.types[0] & AnyMem) ? 0 : 1;
if ((i.tm.operand_types[mem_op] & EsSeg) != 0)
{
if (i.seg[0] != NULL && i.seg[0] != &es)
{
as_bad (_("`%s' operand %d must use `%%es' segment"),
i.tm.name,
mem_op + 1);
return;
}
/* There's only ever one segment override allowed per instruction.
This instruction possibly has a legal segment override on the
second operand, so copy the segment to where non-string
instructions store it, allowing common code. */
i.seg[0] = i.seg[1];
}
else if ((i.tm.operand_types[mem_op + 1] & EsSeg) != 0)
{
if (i.seg[1] != NULL && i.seg[1] != &es)
{
as_bad (_("`%s' operand %d must use `%%es' segment"),
i.tm.name,
mem_op + 2);
return;
}
}
}
/* If matched instruction specifies an explicit instruction mnemonic
suffix, use it. */
if (i.tm.opcode_modifier & (Size16 | Size32 | Size64))
{
if (i.tm.opcode_modifier & Size16)
i.suffix = WORD_MNEM_SUFFIX;
else if (i.tm.opcode_modifier & Size64)
i.suffix = QWORD_MNEM_SUFFIX;
else
i.suffix = LONG_MNEM_SUFFIX;
}
else if (i.reg_operands)
{
/* If there's no instruction mnemonic suffix we try to invent one
based on register operands. */
if (!i.suffix)
{
/* We take i.suffix from the last register operand specified,
Destination register type is more significant than source
register type. */
int op;
for (op = i.operands; --op >= 0;)
if ((i.types[op] & Reg)
&& !(i.tm.operand_types[op] & InOutPortReg))
{
i.suffix = ((i.types[op] & Reg8) ? BYTE_MNEM_SUFFIX :
(i.types[op] & Reg16) ? WORD_MNEM_SUFFIX :
(i.types[op] & Reg64) ? QWORD_MNEM_SUFFIX :
LONG_MNEM_SUFFIX);
break;
}
}
else if (i.suffix == BYTE_MNEM_SUFFIX)
{
int op;
for (op = i.operands; --op >= 0;)
{
/* If this is an eight bit register, it's OK. If it's
the 16 or 32 bit version of an eight bit register,
we will just use the low portion, and that's OK too. */
if (i.types[op] & Reg8)
continue;
/* movzx and movsx should not generate this warning. */
if (intel_syntax
&& (i.tm.base_opcode == 0xfb7
|| i.tm.base_opcode == 0xfb6
|| i.tm.base_opcode == 0x63
|| i.tm.base_opcode == 0xfbe
|| i.tm.base_opcode == 0xfbf))
continue;
if ((i.types[op] & WordReg) && i.op[op].regs->reg_num < 4
#if 0
/* Check that the template allows eight bit regs
This kills insns such as `orb $1,%edx', which
maybe should be allowed. */
&& (i.tm.operand_types[op] & (Reg8|InOutPortReg))
#endif
)
{
/* Prohibit these changes in the 64bit mode, since
the lowering is more complicated. */
if (flag_code == CODE_64BIT
&& (i.tm.operand_types[op] & InOutPortReg) == 0)
as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
i.op[op].regs->reg_name,
i.suffix);
#if REGISTER_WARNINGS
if (!quiet_warnings
&& (i.tm.operand_types[op] & InOutPortReg) == 0)
as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
(i.op[op].regs
+ (i.types[op] & Reg16
? REGNAM_AL - REGNAM_AX
: REGNAM_AL - REGNAM_EAX))->reg_name,
i.op[op].regs->reg_name,
i.suffix);
#endif
continue;
}
/* Any other register is bad. */
if (i.types[op] & (Reg | RegMMX | RegXMM
| SReg2 | SReg3
| Control | Debug | Test
| FloatReg | FloatAcc))
{
as_bad (_("`%%%s' not allowed with `%s%c'"),
i.op[op].regs->reg_name,
i.tm.name,
i.suffix);
return;
}
}
}
else if (i.suffix == LONG_MNEM_SUFFIX)
{
int op;
for (op = i.operands; --op >= 0;)
/* Reject eight bit registers, except where the template
requires them. (eg. movzb) */
if ((i.types[op] & Reg8) != 0
&& (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
{
as_bad (_("`%%%s' not allowed with `%s%c'"),
i.op[op].regs->reg_name,
i.tm.name,
i.suffix);
return;
}
/* Warn if the e prefix on a general reg is missing. */
else if ((!quiet_warnings || flag_code == CODE_64BIT)
&& (i.types[op] & Reg16) != 0
&& (i.tm.operand_types[op] & (Reg32|Acc)) != 0)
{
/* Prohibit these changes in the 64bit mode, since
the lowering is more complicated. */
if (flag_code == CODE_64BIT)
as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
i.op[op].regs->reg_name,
i.suffix);
#if REGISTER_WARNINGS
else
as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
(i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
i.op[op].regs->reg_name,
i.suffix);
#endif
}
/* Warn if the r prefix on a general reg is missing. */
else if ((i.types[op] & Reg64) != 0
&& (i.tm.operand_types[op] & (Reg32|Acc)) != 0)
{
as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
i.op[op].regs->reg_name,
i.suffix);
}
}
else if (i.suffix == QWORD_MNEM_SUFFIX)
{
int op;
for (op = i.operands; --op >= 0; )
/* Reject eight bit registers, except where the template
requires them. (eg. movzb) */
if ((i.types[op] & Reg8) != 0
&& (i.tm.operand_types[op] & (Reg16|Reg32|Acc)) != 0)
{
as_bad (_("`%%%s' not allowed with `%s%c'"),
i.op[op].regs->reg_name,
i.tm.name,
i.suffix);
return;
}
/* Warn if the e prefix on a general reg is missing. */
else if (((i.types[op] & Reg16) != 0
|| (i.types[op] & Reg32) != 0)
&& (i.tm.operand_types[op] & (Reg32|Acc)) != 0)
{
/* Prohibit these changes in the 64bit mode, since
the lowering is more complicated. */
as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
i.op[op].regs->reg_name,
i.suffix);
}
}
else if (i.suffix == WORD_MNEM_SUFFIX)
{
int op;
for (op = i.operands; --op >= 0;)
/* Reject eight bit registers, except where the template
requires them. (eg. movzb) */
if ((i.types[op] & Reg8) != 0
&& (i.tm.operand_types[op] & (Reg16|Reg32|Acc)) != 0)
{
as_bad (_("`%%%s' not allowed with `%s%c'"),
i.op[op].regs->reg_name,
i.tm.name,
i.suffix);
return;
}
/* Warn if the e prefix on a general reg is present. */
else if ((!quiet_warnings || flag_code == CODE_64BIT)
&& (i.types[op] & Reg32) != 0
&& (i.tm.operand_types[op] & (Reg16|Acc)) != 0)
{
/* Prohibit these changes in the 64bit mode, since
the lowering is more complicated. */
if (flag_code == CODE_64BIT)
as_bad (_("Incorrect register `%%%s' used with`%c' suffix"),
i.op[op].regs->reg_name,
i.suffix);
else
#if REGISTER_WARNINGS
as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
(i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
i.op[op].regs->reg_name,
i.suffix);
#endif
}
}
else if (intel_syntax && (i.tm.opcode_modifier & IgnoreSize))
/* Do nothing if the instruction is going to ignore the prefix. */
;
else
abort ();
}
else if ((i.tm.opcode_modifier & DefaultSize) && !i.suffix)
{
i.suffix = stackop_size;
}
/* Make still unresolved immediate matches conform to size of immediate
given in i.suffix. Note: overlap2 cannot be an immediate! */
if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32 | Imm32S))
&& overlap0 != Imm8 && overlap0 != Imm8S
&& overlap0 != Imm16 && overlap0 != Imm32S
&& overlap0 != Imm32 && overlap0 != Imm64)
{
if (i.suffix)
{
overlap0 &= (i.suffix == BYTE_MNEM_SUFFIX ? (Imm8 | Imm8S) :
(i.suffix == WORD_MNEM_SUFFIX ? Imm16 :
(i.suffix == QWORD_MNEM_SUFFIX ? Imm64 | Imm32S : Imm32)));
}
else if (overlap0 == (Imm16 | Imm32S | Imm32)
|| overlap0 == (Imm16 | Imm32)
|| overlap0 == (Imm16 | Imm32S))
{
overlap0 =
((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) ? Imm16 : Imm32S;
}
if (overlap0 != Imm8 && overlap0 != Imm8S
&& overlap0 != Imm16 && overlap0 != Imm32S
&& overlap0 != Imm32 && overlap0 != Imm64)
{
as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
return;
}
}
if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32S | Imm32))
&& overlap1 != Imm8 && overlap1 != Imm8S
&& overlap1 != Imm16 && overlap1 != Imm32S
&& overlap1 != Imm32 && overlap1 != Imm64)
{
if (i.suffix)
{
overlap1 &= (i.suffix == BYTE_MNEM_SUFFIX ? (Imm8 | Imm8S) :
(i.suffix == WORD_MNEM_SUFFIX ? Imm16 :
(i.suffix == QWORD_MNEM_SUFFIX ? Imm64 | Imm32S : Imm32)));
}
else if (overlap1 == (Imm16 | Imm32 | Imm32S)
|| overlap1 == (Imm16 | Imm32)
|| overlap1 == (Imm16 | Imm32S))
{
overlap1 =
((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)) ? Imm16 : Imm32S;
}
if (overlap1 != Imm8 && overlap1 != Imm8S
&& overlap1 != Imm16 && overlap1 != Imm32S
&& overlap1 != Imm32 && overlap1 != Imm64)
{
as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1, i.suffix);
return;
}
}
assert ((overlap2 & Imm) == 0);
i.types[0] = overlap0;
if (overlap0 & ImplicitRegister)
i.reg_operands--;
if (overlap0 & Imm1)
i.imm_operands = 0; /* kludge for shift insns. */
i.types[1] = overlap1;
if (overlap1 & ImplicitRegister)
i.reg_operands--;
i.types[2] = overlap2;
if (overlap2 & ImplicitRegister)
i.reg_operands--;
/* Finalize opcode. First, we change the opcode based on the operand
size given by i.suffix: We need not change things for byte insns. */
if (!i.suffix && (i.tm.opcode_modifier & W))
{
as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
return;
}
/* For movzx and movsx, need to check the register type. */
if (intel_syntax
&& (i.tm.base_opcode == 0xfb6 || i.tm.base_opcode == 0xfbe))
if (i.suffix && i.suffix == BYTE_MNEM_SUFFIX)
{
unsigned int prefix = DATA_PREFIX_OPCODE;
if ((i.op[1].regs->reg_type & Reg16) != 0)
if (!add_prefix (prefix))
return;
}
if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX)
{
/* It's not a byte, select word/dword operation. */
if (i.tm.opcode_modifier & W)
{
if (i.tm.opcode_modifier & ShortForm)
i.tm.base_opcode |= 8;
else
i.tm.base_opcode |= 1;
}
/* Now select between word & dword operations via the operand
size prefix, except for instructions that will ignore this
prefix anyway. */
if (i.suffix != QWORD_MNEM_SUFFIX
&& (i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
&& !(i.tm.opcode_modifier & IgnoreSize))
{
unsigned int prefix = DATA_PREFIX_OPCODE;
if (i.tm.opcode_modifier & JumpByte) /* jcxz, loop */
prefix = ADDR_PREFIX_OPCODE;
if (! add_prefix (prefix))
return;
}
/* Set mode64 for an operand. */
if (i.suffix == QWORD_MNEM_SUFFIX
&& !(i.tm.opcode_modifier & NoRex64))
{
i.rex.mode64 = 1;
if (flag_code < CODE_64BIT)
{
as_bad (_("64bit operations available only in 64bit modes."));
return;
}
}
/* Size floating point instruction. */
if (i.suffix == LONG_MNEM_SUFFIX)
{
if (i.tm.opcode_modifier & FloatMF)
i.tm.base_opcode ^= 4;
}
}
if (i.tm.opcode_modifier & ImmExt)
{
/* These AMD 3DNow! and Intel Katmai New Instructions have an
opcode suffix which is coded in the same place as an 8-bit
immediate field would be. Here we fake an 8-bit immediate
operand from the opcode suffix stored in tm.extension_opcode. */
expressionS *exp;
assert (i.imm_operands == 0 && i.operands <= 2 && 2 < MAX_OPERANDS);
exp = &im_expressions[i.imm_operands++];
i.op[i.operands].imms = exp;
i.types[i.operands++] = Imm8;
exp->X_op = O_constant;
exp->X_add_number = i.tm.extension_opcode;
i.tm.extension_opcode = None;
}
/* For insns with operands there are more diddles to do to the opcode. */
if (i.operands)
{
/* Default segment register this instruction will use
for memory accesses. 0 means unknown.
This is only for optimizing out unnecessary segment overrides. */
const seg_entry *default_seg = 0;
/* The imul $imm, %reg instruction is converted into
imul $imm, %reg, %reg, and the clr %reg instruction
is converted into xor %reg, %reg. */
if (i.tm.opcode_modifier & regKludge)
{
unsigned int first_reg_op = (i.types[0] & Reg) ? 0 : 1;
/* Pretend we saw the extra register operand. */
assert (i.op[first_reg_op + 1].regs == 0);
i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
i.types[first_reg_op + 1] = i.types[first_reg_op];
i.reg_operands = 2;
}
if (i.tm.opcode_modifier & ShortForm)
{
/* The register or float register operand is in operand 0 or 1. */
unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1;
/* Register goes in low 3 bits of opcode. */
i.tm.base_opcode |= i.op[op].regs->reg_num;
if (i.op[op].regs->reg_flags & RegRex)
i.rex.extZ = 1;
if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
{
/* Warn about some common errors, but press on regardless.
The first case can be generated by gcc (<= 2.8.1). */
if (i.operands == 2)
{
/* Reversed arguments on faddp, fsubp, etc. */
as_warn (_("translating to `%s %%%s,%%%s'"), i.tm.name,
i.op[1].regs->reg_name,
i.op[0].regs->reg_name);
}
else
{
/* Extraneous `l' suffix on fp insn. */
as_warn (_("translating to `%s %%%s'"), i.tm.name,
i.op[0].regs->reg_name);
}
}
}
else if (i.tm.opcode_modifier & Modrm)
{
/* The opcode is completed (modulo i.tm.extension_opcode which
must be put into the modrm byte).
Now, we make the modrm & index base bytes based on all the
info we've collected. */
/* i.reg_operands MUST be the number of real register operands;
implicit registers do not count. */
if (i.reg_operands == 2)
{
unsigned int source, dest;
source = ((i.types[0]
& (Reg | RegMMX | RegXMM
| SReg2 | SReg3
| Control | Debug | Test))
? 0 : 1);
dest = source + 1;
i.rm.mode = 3;
/* One of the register operands will be encoded in the
i.tm.reg field, the other in the combined i.tm.mode
and i.tm.regmem fields. If no form of this
instruction supports a memory destination operand,
then we assume the source operand may sometimes be
a memory operand and so we need to store the
destination in the i.rm.reg field. */
if ((i.tm.operand_types[dest] & AnyMem) == 0)
{
i.rm.reg = i.op[dest].regs->reg_num;
i.rm.regmem = i.op[source].regs->reg_num;
if (i.op[dest].regs->reg_flags & RegRex)
i.rex.extX = 1;
if (i.op[source].regs->reg_flags & RegRex)
i.rex.extZ = 1;
}
else
{
i.rm.reg = i.op[source].regs->reg_num;
i.rm.regmem = i.op[dest].regs->reg_num;
if (i.op[dest].regs->reg_flags & RegRex)
i.rex.extZ = 1;
if (i.op[source].regs->reg_flags & RegRex)
i.rex.extX = 1;
}
}
else
{ /* If it's not 2 reg operands... */
if (i.mem_operands)
{
unsigned int fake_zero_displacement = 0;
unsigned int op = ((i.types[0] & AnyMem)
? 0
: (i.types[1] & AnyMem) ? 1 : 2);
default_seg = &ds;
if (! i.base_reg)
{
i.rm.mode = 0;
if (! i.disp_operands)
fake_zero_displacement = 1;
if (! i.index_reg)
{
/* Operand is just <disp> */
if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
{
i.rm.regmem = NO_BASE_REGISTER_16;
i.types[op] &= ~Disp;
i.types[op] |= Disp16;
}
else if (flag_code != CODE_64BIT)
{
i.rm.regmem = NO_BASE_REGISTER;
i.types[op] &= ~Disp;
i.types[op] |= Disp32;
}
else
{
/* 64bit mode overwrites the 32bit
absolute addressing by RIP relative
addressing and absolute addressing
is encoded by one of the redundant
SIB forms. */
i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
i.sib.base = NO_BASE_REGISTER;
i.sib.index = NO_INDEX_REGISTER;
i.types[op] &= ~Disp;
i.types[op] |= Disp32S;
}
}
else /* ! i.base_reg && i.index_reg */
{
i.sib.index = i.index_reg->reg_num;
i.sib.base = NO_BASE_REGISTER;
i.sib.scale = i.log2_scale_factor;
i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
i.types[op] &= ~Disp;
if (flag_code != CODE_64BIT)
i.types[op] |= Disp32; /* Must be 32 bit */
else
i.types[op] |= Disp32S;
if (i.index_reg->reg_flags & RegRex)
i.rex.extY = 1;
}
}
/* RIP addressing for 64bit mode. */
else if (i.base_reg->reg_type == BaseIndex)
{
i.rm.regmem = NO_BASE_REGISTER;
i.types[op] &= ~Disp;
i.types[op] |= Disp32S;
i.flags[op] = Operand_PCrel;
}
else if (i.base_reg->reg_type & Reg16)
{
switch (i.base_reg->reg_num)
{
case 3: /* (%bx) */
if (! i.index_reg)
i.rm.regmem = 7;
else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
i.rm.regmem = i.index_reg->reg_num - 6;
break;
case 5: /* (%bp) */
default_seg = &ss;
if (! i.index_reg)
{
i.rm.regmem = 6;
if ((i.types[op] & Disp) == 0)
{
/* fake (%bp) into 0(%bp) */
i.types[op] |= Disp8;
fake_zero_displacement = 1;
}
}
else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
i.rm.regmem = i.index_reg->reg_num - 6 + 2;
break;
default: /* (%si) -> 4 or (%di) -> 5 */
i.rm.regmem = i.base_reg->reg_num - 6 + 4;
}
i.rm.mode = mode_from_disp_size (i.types[op]);
}
else /* i.base_reg and 32/64 bit mode */
{
if (flag_code == CODE_64BIT
&& (i.types[op] & Disp))
{
if (i.types[op] & Disp8)
i.types[op] = Disp8 | Disp32S;
else
i.types[op] = Disp32S;
}
i.rm.regmem = i.base_reg->reg_num;
if (i.base_reg->reg_flags & RegRex)
i.rex.extZ = 1;
i.sib.base = i.base_reg->reg_num;
/* x86-64 ignores REX prefix bit here to avoid
decoder complications. */
if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
{
default_seg = &ss;
if (i.disp_operands == 0)
{
fake_zero_displacement = 1;
i.types[op] |= Disp8;
}
}
else if (i.base_reg->reg_num == ESP_REG_NUM)
{
default_seg = &ss;
}
i.sib.scale = i.log2_scale_factor;
if (! i.index_reg)
{
/* <disp>(%esp) becomes two byte modrm
with no index register. We've already
stored the code for esp in i.rm.regmem
ie. ESCAPE_TO_TWO_BYTE_ADDRESSING. Any
base register besides %esp will not use
the extra modrm byte. */
i.sib.index = NO_INDEX_REGISTER;
#if ! SCALE1_WHEN_NO_INDEX
/* Another case where we force the second
modrm byte. */
if (i.log2_scale_factor)
i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
#endif
}
else
{
i.sib.index = i.index_reg->reg_num;
i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
if (i.index_reg->reg_flags & RegRex)
i.rex.extY = 1;
}
i.rm.mode = mode_from_disp_size (i.types[op]);
}
if (fake_zero_displacement)
{
/* Fakes a zero displacement assuming that i.types[op]
holds the correct displacement size. */
expressionS *exp;
assert (i.op[op].disps == 0);
exp = &disp_expressions[i.disp_operands++];
i.op[op].disps = exp;
exp->X_op = O_constant;
exp->X_add_number = 0;
exp->X_add_symbol = (symbolS *) 0;
exp->X_op_symbol = (symbolS *) 0;
}
}
/* Fill in i.rm.reg or i.rm.regmem field with register
operand (if any) based on i.tm.extension_opcode.
Again, we must be careful to make sure that
segment/control/debug/test/MMX registers are coded
into the i.rm.reg field. */
if (i.reg_operands)
{
unsigned int op =
((i.types[0]
& (Reg | RegMMX | RegXMM
| SReg2 | SReg3
| Control | Debug | Test))
? 0
: ((i.types[1]
& (Reg | RegMMX | RegXMM
| SReg2 | SReg3
| Control | Debug | Test))
? 1
: 2));
/* If there is an extension opcode to put here, the
register number must be put into the regmem field. */
if (i.tm.extension_opcode != None)
{
i.rm.regmem = i.op[op].regs->reg_num;
if (i.op[op].regs->reg_flags & RegRex)
i.rex.extZ = 1;
}
else
{
i.rm.reg = i.op[op].regs->reg_num;
if (i.op[op].regs->reg_flags & RegRex)
i.rex.extX = 1;
}
/* Now, if no memory operand has set i.rm.mode = 0, 1, 2
we must set it to 3 to indicate this is a register
operand in the regmem field. */
if (!i.mem_operands)
i.rm.mode = 3;
}
/* Fill in i.rm.reg field with extension opcode (if any). */
if (i.tm.extension_opcode != None)
i.rm.reg = i.tm.extension_opcode;
}
}
else if (i.tm.opcode_modifier & (Seg2ShortForm | Seg3ShortForm))
{
if (i.tm.base_opcode == POP_SEG_SHORT
&& i.op[0].regs->reg_num == 1)
{
as_bad (_("you can't `pop %%cs'"));
return;
}
i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
if (i.op