)]}'
{
  "commit": "434deed44de4ea2daaa53f6d38495b9baf2ea9cb",
  "tree": "b073f41793566608d55ac69358d04574b15edbfc",
  "parents": [
    "1fa0873f1d99fc24de0ccc3de486ab8ad4ce966a"
  ],
  "author": {
    "name": "Haochen Jiang",
    "email": "haochen.jiang@intel.com",
    "time": "Thu Jan 02 10:17:39 2025 +0800"
  },
  "committer": {
    "name": "Haochen Jiang",
    "email": "haochen.jiang@intel.com",
    "time": "Thu Jan 02 10:17:39 2025 +0800"
  },
  "message": "Support Intel AMX-TF32\n\nIn this patch, we will support AMX-TF32. It is a simple ISA\ncomparing to the previous ones, so there is no special handling.\n\ngas/ChangeLog:\n\n\t* config/tc-i386.c: Add amx_tf32.\n\t* doc/c-i386.texi: Document .amx_tf32.\n\t* testsuite/gas/i386/x86-64.exp: Run AMX-TF32 tests.\n\t* testsuite/gas/i386/x86-64-amx-tf32-bad.d: New test.\n\t* testsuite/gas/i386/x86-64-amx-tf32-bad.s: Ditto.\n\t* testsuite/gas/i386/x86-64-amx-tf32-intel.d: Ditto.\n\t* testsuite/gas/i386/x86-64-amx-tf32-inval.l: Ditto.\n\t* testsuite/gas/i386/x86-64-amx-tf32-inval.s: Ditto.\n\t* testsuite/gas/i386/x86-64-amx-tf32.d: Ditto.\n\t* testsuite/gas/i386/x86-64-amx-tf32.s: Ditto.\n\nopcodes/ChangeLog:\n\n\t* i386-dis.c (PREFIX_VEX_0F3848_X86_64_W_0_L_0): New.\n\t(X86_64_VEX_0F3848): Ditto.\n\t(VEX_LEN_0F3848_X86_64_W_0): Ditto.\n\t(VEX_W_0F3848_X86_64): Ditto.\n\t(prefix_table): Add PREFIX_VEX_0F3848_X86_64_W_0_L_0.\n\t(x86_64_table): Add X86_64_VEX_0F3848.\n\t(vex_len_table): Add VEX_LEN_0F3848_X86_64_W_0.\n\t(vex_w_table): Add VEX_W_0F3848_X86_64.\n\t* i386-gen.c (isa_dependencies): Add AMX_TF32.\n\t(cpu_flags): Ditto.\n\t* i386-init.h: Regenerated.\n\t* i386-mnem.h: Ditto.\n\t* i386-opc.h (CpuAMX_TF32): New.\n\t(i386_cpu_flags): Add cpuamx_tf32.\n\t* i386-opc.tbl: Add AMX-TF32 instructions.\n\t* i386-tbl.h: Regenerated.\n",
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