)]}'
{
  "commit": "477904ca751c50d243ee3cba3f12cf75e8ba12b3",
  "tree": "c8cc726797b77cc277f6ef04f51aa5deda085dfd",
  "parents": [
    "49fffa58f7e6da777d10fe77663bc7c8f531fe7f"
  ],
  "author": {
    "name": "Jeff Law",
    "email": "jeffreyalaw@gmail.com",
    "time": "Wed Apr 06 11:10:40 2022 -0400"
  },
  "committer": {
    "name": "Jeff Law",
    "email": "jeffreyalaw@gmail.com",
    "time": "Wed Apr 06 11:10:40 2022 -0400"
  },
  "message": "Fix for v850e divq instruction\n\nThis is the last of the correctness fixes I\u0027ve been carrying around for the\nv850.\n\nLike the other recent fixes, this is another case where we haven\u0027t been as\ncareful as we should WRT host vs target types.   For the divq instruction\nboth operands are 32 bit types.  Yet in the simulator code we convert them\nfrom unsigned int to signed long by assignment.  So 0xfffffffb (aka -5)\nturns into 4294967291 and naturally that changes the result of our division.\n\nThe fix is simple, insert a cast to int32_t to force interpretation as a\nsigned value.\n\nTestcase for the simulator is included.  It has a trivial dependency on the\nbins patch.\n",
  "tree_diff": [
    {
      "type": "add",
      "old_id": "0000000000000000000000000000000000000000",
      "old_mode": 0,
      "old_path": "/dev/null",
      "new_id": "8461f86f7a0d885fcf23cd48c882a810ee31e70e",
      "new_mode": 33188,
      "new_path": "sim/testsuite/v850/divq.cgs"
    },
    {
      "type": "modify",
      "old_id": "e9a5d489d887b29f019d7ce51c5e527eae37a17e",
      "old_mode": 33188,
      "old_path": "sim/v850/simops.c",
      "new_id": "f90a0f7573cfb837d940a0f198f9e4755b652452",
      "new_mode": 33188,
      "new_path": "sim/v850/simops.c"
    }
  ]
}