)]}'
{
  "commit": "503fae12992e5dbf48b4e30cea8d35f31d87effe",
  "tree": "c1bd390a4f96d3ac0632de6ce917683fccf56667",
  "parents": [
    "586c62819f6eb9a77978628afd53ba12c91a11e7"
  ],
  "author": {
    "name": "Richard Sandiford",
    "email": "richard.sandiford@arm.com",
    "time": "Thu Mar 30 11:09:11 2023 +0100"
  },
  "committer": {
    "name": "Richard Sandiford",
    "email": "richard.sandiford@arm.com",
    "time": "Thu Mar 30 11:09:11 2023 +0100"
  },
  "message": "aarch64: Add support for predicate-as-counter registers\n\nSME2 adds a new format for the existing SVE predicate registers:\npredicates as counters rather than predicates as masks.  In assembly\ncode, operands that interpret predicates as counters are written\npn\u003cN\u003e rather than p\u003cN\u003e.\n\nThis patch adds support for these registers and extends some\nexisting instructions to support them.  Since the new forms\nare just a programmer convenience, there\u0027s no need to make them\nmore restrictive than the earlier predicate-as-mask forms.\n",
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