aarch64: Mark SME mova aliases
This will only change behaviour during disassembly with -M no-aliases.
diff --git a/opcodes/aarch64-asm-2.c b/opcodes/aarch64-asm-2.c
index b4ce5f4..5b92205 100644
--- a/opcodes/aarch64-asm-2.c
+++ b/opcodes/aarch64-asm-2.c
@@ -608,6 +608,46 @@
case 1872: /* sel */
value = 1872; /* --> sel. */
break;
+ case 2420: /* mov */
+ case 2422: /* mova */
+ value = 2422; /* --> mova. */
+ break;
+ case 2421: /* mov */
+ case 2423: /* mova */
+ value = 2423; /* --> mova. */
+ break;
+ case 2646: /* mov */
+ case 2654: /* mova */
+ value = 2654; /* --> mova. */
+ break;
+ case 2647: /* mov */
+ case 2655: /* mova */
+ value = 2655; /* --> mova. */
+ break;
+ case 2648: /* mov */
+ case 2656: /* mova */
+ value = 2656; /* --> mova. */
+ break;
+ case 2649: /* mov */
+ case 2657: /* mova */
+ value = 2657; /* --> mova. */
+ break;
+ case 2650: /* mov */
+ case 2658: /* mova */
+ value = 2658; /* --> mova. */
+ break;
+ case 2651: /* mov */
+ case 2659: /* mova */
+ value = 2659; /* --> mova. */
+ break;
+ case 2652: /* mov */
+ case 2660: /* mova */
+ value = 2660; /* --> mova. */
+ break;
+ case 2653: /* mov */
+ case 2661: /* mova */
+ value = 2661; /* --> mova. */
+ break;
default: return NULL;
}
diff --git a/opcodes/aarch64-dis-2.c b/opcodes/aarch64-dis-2.c
index 84285ff..e876849 100644
--- a/opcodes/aarch64-dis-2.c
+++ b/opcodes/aarch64-dis-2.c
@@ -127,8 +127,8 @@
/* 33222222222211111111110000000000
10987654321098765432109876543210
x1000000xx00000xxxxxxxxxxxxxxxxx
- mov. */
- return 2421;
+ mova. */
+ return 2423;
}
else
{
@@ -201,8 +201,8 @@
/* 33222222222211111111110000000000
10987654321098765432109876543210
x1000000xx0x001xxxxxxx0xxxxxxxxx
- mov. */
- return 2420;
+ mova. */
+ return 2422;
}
else
{
@@ -346,8 +346,8 @@
/* 33222222222211111111110000000000
10987654321098765432109876543210
x1000000xx0x010xxxxx00xxxxxxxxxx
- mov. */
- return 2652;
+ mova. */
+ return 2660;
}
else
{
@@ -356,8 +356,8 @@
/* 33222222222211111111110000000000
10987654321098765432109876543210
x1000000xx0x011xxxxx000xxxxxxxxx
- mov. */
- return 2648;
+ mova. */
+ return 2656;
}
else
{
@@ -583,8 +583,8 @@
/* 33222222222211111111110000000000
10987654321098765432109876543210
x1000000xx0xx10xxxxx10xxxxxxxxxx
- mov. */
- return 2650;
+ mova. */
+ return 2658;
}
else
{
@@ -593,8 +593,8 @@
/* 33222222222211111111110000000000
10987654321098765432109876543210
x1000000xx0xx11xxxxx100xxxxxxxxx
- mov. */
- return 2646;
+ mova. */
+ return 2654;
}
else
{
@@ -616,8 +616,8 @@
/* 33222222222211111111110000000000
10987654321098765432109876543210
x1000000xx0xx10xxxxx01xxxxxxxxxx
- mov. */
- return 2653;
+ mova. */
+ return 2661;
}
else
{
@@ -626,8 +626,8 @@
/* 33222222222211111111110000000000
10987654321098765432109876543210
x1000000xx0xx11xxxxx010xxxxxxxxx
- mov. */
- return 2649;
+ mova. */
+ return 2657;
}
else
{
@@ -679,8 +679,8 @@
/* 33222222222211111111110000000000
10987654321098765432109876543210
x1000000xx0xx10xxxxx11xxxxxxxxxx
- mov. */
- return 2651;
+ mova. */
+ return 2659;
}
else
{
@@ -689,8 +689,8 @@
/* 33222222222211111111110000000000
10987654321098765432109876543210
x1000000xx0xx11xxxxx110xxxxxxxxx
- mov. */
- return 2647;
+ mova. */
+ return 2655;
}
else
{
@@ -34546,26 +34546,6 @@
int value;
switch (key)
{
- case 2421: value = 2423; break; /* mov --> mova. */
- case 2423: return NULL; /* mova --> NULL. */
- case 2420: value = 2422; break; /* mov --> mova. */
- case 2422: return NULL; /* mova --> NULL. */
- case 2652: value = 2660; break; /* mov --> mova. */
- case 2660: return NULL; /* mova --> NULL. */
- case 2648: value = 2656; break; /* mov --> mova. */
- case 2656: return NULL; /* mova --> NULL. */
- case 2650: value = 2658; break; /* mov --> mova. */
- case 2658: return NULL; /* mova --> NULL. */
- case 2646: value = 2654; break; /* mov --> mova. */
- case 2654: return NULL; /* mova --> NULL. */
- case 2653: value = 2661; break; /* mov --> mova. */
- case 2661: return NULL; /* mova --> NULL. */
- case 2649: value = 2657; break; /* mov --> mova. */
- case 2657: return NULL; /* mova --> NULL. */
- case 2651: value = 2659; break; /* mov --> mova. */
- case 2659: return NULL; /* mova --> NULL. */
- case 2647: value = 2655; break; /* mov --> mova. */
- case 2655: return NULL; /* mova --> NULL. */
case 2506: value = 3288; break; /* fclamp --> bfclamp. */
case 3288: return NULL; /* bfclamp --> NULL. */
case 2507: value = 3289; break; /* fclamp --> bfclamp. */
@@ -35019,6 +34999,16 @@
case 1808: value = 1334; break; /* orrs --> movs. */
case 1871: value = 1329; break; /* sel --> mov. */
case 1872: value = 1332; break; /* sel --> mov. */
+ case 2422: value = 2420; break; /* mova --> mov. */
+ case 2423: value = 2421; break; /* mova --> mov. */
+ case 2654: value = 2646; break; /* mova --> mov. */
+ case 2655: value = 2647; break; /* mova --> mov. */
+ case 2656: value = 2648; break; /* mova --> mov. */
+ case 2657: value = 2649; break; /* mova --> mov. */
+ case 2658: value = 2650; break; /* mova --> mov. */
+ case 2659: value = 2651; break; /* mova --> mov. */
+ case 2660: value = 2652; break; /* mova --> mov. */
+ case 2661: value = 2653; break; /* mova --> mov. */
default: return NULL;
}
@@ -35218,6 +35208,16 @@
case 1334: value = 1808; break; /* movs --> orrs. */
case 1329: value = 1871; break; /* mov --> sel. */
case 1332: value = 1872; break; /* mov --> sel. */
+ case 2420: value = 2422; break; /* mov --> mova. */
+ case 2421: value = 2423; break; /* mov --> mova. */
+ case 2646: value = 2654; break; /* mov --> mova. */
+ case 2647: value = 2655; break; /* mov --> mova. */
+ case 2648: value = 2656; break; /* mov --> mova. */
+ case 2649: value = 2657; break; /* mov --> mova. */
+ case 2650: value = 2658; break; /* mov --> mova. */
+ case 2651: value = 2659; break; /* mov --> mova. */
+ case 2652: value = 2660; break; /* mov --> mova. */
+ case 2653: value = 2661; break; /* mov --> mova. */
default: return NULL;
}
diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h
index 70cf2e4..f735899 100644
--- a/opcodes/aarch64-tbl.h
+++ b/opcodes/aarch64-tbl.h
@@ -5802,10 +5802,10 @@
SME_INSN ("usmops", 0xa1800010, 0xffe0001c, sme_misc, 0, OP5 (SME_ZAda_2b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SVE_SMMBB, 0, 0),
SME_I16I64_INSN ("usmops", 0xa1c00010, 0xffe00018, sme_misc, 0, OP5 (SME_ZAda_3b, SVE_Pg3, SME_Pm, SVE_Zn, SVE_Zm_16), OP_SVE_DMMHH, 0, 0),
- SME_INSN ("mov", 0xc0020000, 0xff3e0200, sme_mov, 0, OP3 (SVE_Zd, SVE_Pg3, SME_ZA_HV_idx_src), OP_SVE_VMV_BHSDQ, 0, 0),
- SME_INSN ("mov", 0xc0000000, 0xff3e0010, sme_mov, 0, OP3 (SME_ZA_HV_idx_dest, SVE_Pg3, SVE_Zn), OP_SVE_VMV_BHSDQ, 0, 0),
- SME_INSN ("mova", 0xc0020000, 0xff3e0200, sme_mov, 0, OP3 (SVE_Zd, SVE_Pg3, SME_ZA_HV_idx_src), OP_SVE_VMV_BHSDQ, 0, 0),
- SME_INSN ("mova", 0xc0000000, 0xff3e0010, sme_mov, 0, OP3 (SME_ZA_HV_idx_dest, SVE_Pg3, SVE_Zn), OP_SVE_VMV_BHSDQ, 0, 0),
+ SME_INSN ("mov", 0xc0020000, 0xff3e0200, sme_mov, 0, OP3 (SVE_Zd, SVE_Pg3, SME_ZA_HV_idx_src), OP_SVE_VMV_BHSDQ, F_ALIAS, 0),
+ SME_INSN ("mov", 0xc0000000, 0xff3e0010, sme_mov, 0, OP3 (SME_ZA_HV_idx_dest, SVE_Pg3, SVE_Zn), OP_SVE_VMV_BHSDQ, F_ALIAS, 0),
+ SME_INSN ("mova", 0xc0020000, 0xff3e0200, sme_mov, 0, OP3 (SVE_Zd, SVE_Pg3, SME_ZA_HV_idx_src), OP_SVE_VMV_BHSDQ, F_HAS_ALIAS, 0),
+ SME_INSN ("mova", 0xc0000000, 0xff3e0010, sme_mov, 0, OP3 (SME_ZA_HV_idx_dest, SVE_Pg3, SVE_Zn), OP_SVE_VMV_BHSDQ, F_HAS_ALIAS, 0),
SME_INSN ("zero", 0xc0080000, 0xffffff00, sme_misc, 0, OP1 (SME_list_of_64bit_tiles), {}, 0, 0),
@@ -6040,22 +6040,22 @@
SME2_INSN ("luti4", 0xc0ca0000, 0xfffe0c00, sme_size_12_bhs, 0, OP3 (SVE_Zd, SME_ZT0, SME_Zn_INDEX3_14), OP_SVE_VUU_BHS, 0, 0),
SME2_INSN ("luti4", 0xc08a4000, 0xfffe4c01, sme_size_12_bhs, 0, OP3 (SME_Zdnx2, SME_ZT0, SME_Zn_INDEX2_15), OP_SVE_VUU_BHS, 0, 0),
SME2_INSN ("luti4", 0xc08a8000, 0xfffecc03, sme_size_12_hs, 0, OP3 (SME_Zdnx4, SME_ZT0, SME_Zn_INDEX1_16), OP_SVE_VUU_HS, 0, 0),
- SME2_INSN ("mov", 0xc0060800, 0xffff9f01, sme2_mov, 0, OP2 (SME_Zdnx2, SME_ZA_array_off3_5), OP_SVE_VV_BHSD, F_OD (2), 0),
- SME2_INSN ("mov", 0xc0060c00, 0xffff9f03, sme2_mov, 0, OP2 (SME_Zdnx4, SME_ZA_array_off3_5), OP_SVE_VV_BHSD, F_OD (4), 0),
- SME2_INSN ("mov", 0xc0060000, 0xff3f1f01, sme_size_22, 0, OP2 (SME_Zdnx2, SME_ZA_HV_idx_srcxN), OP_SVE_VV_BHSDQ, F_OD (2), 0),
- SME2_INSN ("mov", 0xc0060400, 0xff3f1f03, sme_size_22, 0, OP2 (SME_Zdnx4, SME_ZA_HV_idx_srcxN), OP_SVE_VV_BHSDQ, F_OD (4), 0),
- SME2_INSN ("mov", 0xc0040800, 0xffff9c38, sme2_mov, 0, OP2 (SME_ZA_array_off3_0, SME_Znx2), OP_SVE_VV_BHSD, F_OD (2), 0),
- SME2_INSN ("mov", 0xc0040c00, 0xffff9c78, sme2_mov, 0, OP2 (SME_ZA_array_off3_0, SME_Znx4), OP_SVE_VV_BHSD, F_OD (4), 0),
- SME2_INSN ("mov", 0xc0040000, 0xff3f1c38, sme_size_22, 0, OP2 (SME_ZA_HV_idx_destxN, SME_Znx2), OP_SVE_VV_BHSDQ, F_OD (2), 0),
- SME2_INSN ("mov", 0xc0040400, 0xff3f1c78, sme_size_22, 0, OP2 (SME_ZA_HV_idx_destxN, SME_Znx4), OP_SVE_VV_BHSDQ, F_OD (4), 0),
- SME2_INSN ("mova", 0xc0060800, 0xffff9f01, sme2_mov, 0, OP2 (SME_Zdnx2, SME_ZA_array_off3_5), OP_SVE_VV_BHSD, F_OD (2), 0),
- SME2_INSN ("mova", 0xc0060c00, 0xffff9f03, sme2_mov, 0, OP2 (SME_Zdnx4, SME_ZA_array_off3_5), OP_SVE_VV_BHSD, F_OD (4), 0),
- SME2_INSN ("mova", 0xc0060000, 0xff3f1f01, sme_size_22, 0, OP2 (SME_Zdnx2, SME_ZA_HV_idx_srcxN), OP_SVE_VV_BHSDQ, F_OD (2), 0),
- SME2_INSN ("mova", 0xc0060400, 0xff3f1f03, sme_size_22, 0, OP2 (SME_Zdnx4, SME_ZA_HV_idx_srcxN), OP_SVE_VV_BHSDQ, F_OD (4), 0),
- SME2_INSN ("mova", 0xc0040800, 0xffff9c38, sme2_mov, 0, OP2 (SME_ZA_array_off3_0, SME_Znx2), OP_SVE_VV_BHSD, F_OD (2), 0),
- SME2_INSN ("mova", 0xc0040c00, 0xffff9c78, sme2_mov, 0, OP2 (SME_ZA_array_off3_0, SME_Znx4), OP_SVE_VV_BHSD, F_OD (4), 0),
- SME2_INSN ("mova", 0xc0040000, 0xff3f1c38, sme_size_22, 0, OP2 (SME_ZA_HV_idx_destxN, SME_Znx2), OP_SVE_VV_BHSDQ, F_OD (2), 0),
- SME2_INSN ("mova", 0xc0040400, 0xff3f1c78, sme_size_22, 0, OP2 (SME_ZA_HV_idx_destxN, SME_Znx4), OP_SVE_VV_BHSDQ, F_OD (4), 0),
+ SME2_INSN ("mov", 0xc0060800, 0xffff9f01, sme2_mov, 0, OP2 (SME_Zdnx2, SME_ZA_array_off3_5), OP_SVE_VV_BHSD, F_OD (2) | F_ALIAS, 0),
+ SME2_INSN ("mov", 0xc0060c00, 0xffff9f03, sme2_mov, 0, OP2 (SME_Zdnx4, SME_ZA_array_off3_5), OP_SVE_VV_BHSD, F_OD (4) | F_ALIAS, 0),
+ SME2_INSN ("mov", 0xc0060000, 0xff3f1f01, sme_size_22, 0, OP2 (SME_Zdnx2, SME_ZA_HV_idx_srcxN), OP_SVE_VV_BHSDQ, F_OD (2) | F_ALIAS, 0),
+ SME2_INSN ("mov", 0xc0060400, 0xff3f1f03, sme_size_22, 0, OP2 (SME_Zdnx4, SME_ZA_HV_idx_srcxN), OP_SVE_VV_BHSDQ, F_OD (4) | F_ALIAS, 0),
+ SME2_INSN ("mov", 0xc0040800, 0xffff9c38, sme2_mov, 0, OP2 (SME_ZA_array_off3_0, SME_Znx2), OP_SVE_VV_BHSD, F_OD (2) | F_ALIAS, 0),
+ SME2_INSN ("mov", 0xc0040c00, 0xffff9c78, sme2_mov, 0, OP2 (SME_ZA_array_off3_0, SME_Znx4), OP_SVE_VV_BHSD, F_OD (4) | F_ALIAS, 0),
+ SME2_INSN ("mov", 0xc0040000, 0xff3f1c38, sme_size_22, 0, OP2 (SME_ZA_HV_idx_destxN, SME_Znx2), OP_SVE_VV_BHSDQ, F_OD (2) | F_ALIAS, 0),
+ SME2_INSN ("mov", 0xc0040400, 0xff3f1c78, sme_size_22, 0, OP2 (SME_ZA_HV_idx_destxN, SME_Znx4), OP_SVE_VV_BHSDQ, F_OD (4) | F_ALIAS, 0),
+ SME2_INSN ("mova", 0xc0060800, 0xffff9f01, sme2_mov, 0, OP2 (SME_Zdnx2, SME_ZA_array_off3_5), OP_SVE_VV_BHSD, F_OD (2) | F_HAS_ALIAS, 0),
+ SME2_INSN ("mova", 0xc0060c00, 0xffff9f03, sme2_mov, 0, OP2 (SME_Zdnx4, SME_ZA_array_off3_5), OP_SVE_VV_BHSD, F_OD (4) | F_HAS_ALIAS, 0),
+ SME2_INSN ("mova", 0xc0060000, 0xff3f1f01, sme_size_22, 0, OP2 (SME_Zdnx2, SME_ZA_HV_idx_srcxN), OP_SVE_VV_BHSDQ, F_OD (2) | F_HAS_ALIAS, 0),
+ SME2_INSN ("mova", 0xc0060400, 0xff3f1f03, sme_size_22, 0, OP2 (SME_Zdnx4, SME_ZA_HV_idx_srcxN), OP_SVE_VV_BHSDQ, F_OD (4) | F_HAS_ALIAS, 0),
+ SME2_INSN ("mova", 0xc0040800, 0xffff9c38, sme2_mov, 0, OP2 (SME_ZA_array_off3_0, SME_Znx2), OP_SVE_VV_BHSD, F_OD (2) | F_HAS_ALIAS, 0),
+ SME2_INSN ("mova", 0xc0040c00, 0xffff9c78, sme2_mov, 0, OP2 (SME_ZA_array_off3_0, SME_Znx4), OP_SVE_VV_BHSD, F_OD (4) | F_HAS_ALIAS, 0),
+ SME2_INSN ("mova", 0xc0040000, 0xff3f1c38, sme_size_22, 0, OP2 (SME_ZA_HV_idx_destxN, SME_Znx2), OP_SVE_VV_BHSDQ, F_OD (2) | F_HAS_ALIAS, 0),
+ SME2_INSN ("mova", 0xc0040400, 0xff3f1c78, sme_size_22, 0, OP2 (SME_ZA_HV_idx_destxN, SME_Znx4), OP_SVE_VV_BHSDQ, F_OD (4) | F_HAS_ALIAS, 0),
SME2_INSN ("movt", 0xc04e03e0, 0xffff8fe0, sme_misc, 0, OP2 (SME_ZT0_INDEX, Rt), OP_SVE_UX, 0, 0),
SME2_INSN ("movt", 0xc04c03e0, 0xffff8fe0, sme_misc, 0, OP2 (Rt, SME_ZT0_INDEX), OP_SVE_XU, 0, 0),
SVE2p1_SME2_INSN ("pext", 0x25207010, 0xff3ffc10, sme_size_22, 0, OP2 (SVE_Pd, SME_PNn3_INDEX2), OP_SVE_VU_BHSD, 0, 0),
