)]}'
{
  "commit": "5eeeafe0a6884eaf1c5a21160e78e53842fa7cba",
  "tree": "ccae730941360b00b9870cf3f271701d2e368527",
  "parents": [
    "c34d1cc9200ae24dc7572aaf77d80276c0490e9b"
  ],
  "author": {
    "name": "Jan Beulich",
    "email": "jbeulich@suse.com",
    "time": "Fri Feb 24 13:57:31 2023 +0100"
  },
  "committer": {
    "name": "Jan Beulich",
    "email": "jbeulich@suse.com",
    "time": "Fri Feb 24 13:57:31 2023 +0100"
  },
  "message": "x86: have insns acting on segment selector values allow for consistent operands\n\nWhile MOV to/from segment register as well as selector storing insns\nalready permit 32- and 64-bit GPR operands, selector loading insns and\nARPL do not. Split templates accordingly.\n",
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