)]}'
{
  "commit": "6b84c098e533f87d7973fd6fe8a39ee97255ebdb",
  "tree": "ba56a5585518038f476d3a7e6a4b216e67f0be1e",
  "parents": [
    "83029f7ff5d571dff0190e8d92c26e032c7acd76"
  ],
  "author": {
    "name": "Tsukasa OI",
    "email": "research_trasio@irq.a4lg.com",
    "time": "Tue Jun 28 19:07:52 2022 +0900"
  },
  "committer": {
    "name": "Tsukasa OI",
    "email": "research_trasio@irq.a4lg.com",
    "time": "Fri Oct 28 14:17:34 2022 +0000"
  },
  "message": "RISC-V: Improve \"bits undefined\" diagnostics\n\nThis commit improves internal error message\n\"internal: bad RISC-V opcode (bits 0x%lx undefined): %s %s\"\nto display actual unused bits (excluding non-instruction bits).\n\ngas/ChangeLog:\n\n\t* config/tc-riscv.c (validate_riscv_insn): Exclude non-\n\tinstruction bits from displaying internal diagnostics.\n\tChange error message slightly.\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "70558796c24dee44d450cd950b783b169fa52d1b",
      "old_mode": 33188,
      "old_path": "gas/config/tc-riscv.c",
      "new_id": "3237369f11f9f16c05d21cb1c9813bed8b32b040",
      "new_mode": 33188,
      "new_path": "gas/config/tc-riscv.c"
    }
  ]
}