)]}'
{
  "commit": "6ef35c04dffe685ece08212201c4c032baf8aa86",
  "tree": "3eba01220e92f2f24152d4ad94f4be8c45c9f53b",
  "parents": [
    "7505bb034c7c8a3d9ecf34e22777114c8bc4a93e"
  ],
  "author": {
    "name": "Nick Clifton",
    "email": "nickc@redhat.com",
    "time": "Thu Dec 01 13:09:26 2022 +0000"
  },
  "committer": {
    "name": "Nick Clifton",
    "email": "nickc@redhat.com",
    "time": "Thu Dec 01 13:09:26 2022 +0000"
  },
  "message": "Fix verilog output when the width is \u003e 1.\n\n\tPR 25202\nbfd\t* bfd.c (VerilogDataEndianness): New variable.\n\t(verilog_write_record): Use VerilogDataEndianness, if set, to\n\tchoose the endianness of the output.\n\t(verilog_write_section): Adjust the address by the data width.\n\nbinutils* objcopy.c (copy_object): Set VerilogDataEndianness to the\n\tendianness of the input file.\n\t(copy_main): Verifiy the value set by the --verilog-data-width\n\toption.\n\t* testsuite/binutils-all/objcopy.exp: Add tests of the new behaviour.\n\t* testsuite/binutils-all/verilog-I4.hex: New file.\n",
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