)]}'
{
  "commit": "704b30cbb2beeac1e90c4ee6f1f5b9f1dc2e5ee4",
  "tree": "b05368971f51c38351e0044d3b9199254bc75e02",
  "parents": [
    "d501d384886673b7c3981fe225b2d7719440abda"
  ],
  "author": {
    "name": "Christoph Müllner",
    "email": "christoph.muellner@vrull.eu",
    "time": "Mon Jul 03 12:10:47 2023 +0200"
  },
  "committer": {
    "name": "Nelson Chu",
    "email": "nelson@rivosinc.com",
    "time": "Mon Jul 03 18:17:59 2023 +0800"
  },
  "message": "RISC-V: Zvkh[a,b]: Remove individual instruction class\n\nCurrently we have three instruction classes defined for Zvkh[a,b]:\n- INSN_CLASS_ZVKNHA\n- INSN_CLASS_ZVKNHB\n- INSN_CLASS_ZVKNHA_OR_ZVKNHB\n\nThe encodings of all instructions in Zvknh[a,b] are identical.\nTherefore, we don\u0027t need the individual instruction classes\nand can remove them.\n\nThis patch also adds the missing support of the combined instruction\nclass in riscv_multi_subset_supports_ext().\n\nFixes: 62edb233ef5 (\"RISC-V: Add support for the Zvknh[a,b] ISA extensions\")\nReported-By: Nelson Chu \u003cnelson@rivosinc.com\u003e\nSigned-off-by: Christoph Müllner \u003cchristoph.muellner@vrull.eu\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "d6c8e046e3e687876640fb56245f4180bd14dccd",
      "old_mode": 33188,
      "old_path": "bfd/elfxx-riscv.c",
      "new_id": "bdfc0ef01f4be4dae28fa987d6bfe49b16ca147b",
      "new_mode": 33188,
      "new_path": "bfd/elfxx-riscv.c"
    },
    {
      "type": "modify",
      "old_id": "d859f44fc9259995752d482368e2fe47f9f13d5c",
      "old_mode": 33188,
      "old_path": "include/opcode/riscv.h",
      "new_id": "739d6dafae9db87997055787a04c32c8f02d882a",
      "new_mode": 33188,
      "new_path": "include/opcode/riscv.h"
    }
  ]
}