| //Original:/testcases/core/c_dsp32alu_rl_p/c_dsp32alu_rl_p.dsp | |
| // Spec Reference: dsp32alu dreg (half) | |
| # mach: bfin | |
| .include "testutils.inc" | |
| start | |
| imm32 r0, 0x19678911; | |
| imm32 r1, 0x2799ab1d; | |
| imm32 r2, 0x34945515; | |
| imm32 r3, 0x46967717; | |
| imm32 r4, 0x5678891b; | |
| imm32 r5, 0x6789ab1d; | |
| imm32 r6, 0x74445515; | |
| imm32 r7, 0x86669977; | |
| R0.L = R0.L + R0.L (NS); | |
| R1.L = R0.L + R1.H (NS); | |
| R2.L = R0.H + R2.L (NS); | |
| R3.L = R0.H + R3.H (NS); | |
| R4.L = R0.L + R4.L (NS); | |
| R5.L = R0.L + R5.H (NS); | |
| R6.L = R0.H + R6.L (NS); | |
| R7.L = R0.H + R7.H (NS); | |
| CHECKREG r4, 0x56789B3D; | |
| CHECKREG r5, 0x678979AB; | |
| CHECKREG r6, 0x74446E7C; | |
| CHECKREG r7, 0x86669FCD; | |
| CHECKREG r4, 0x56789B3D; | |
| CHECKREG r5, 0x678979AB; | |
| CHECKREG r6, 0x74446E7C; | |
| CHECKREG r7, 0x86669FCD; | |
| imm32 r0, 0x15678911; | |
| imm32 r1, 0xaa89ab1d; | |
| imm32 r2, 0x34445515; | |
| imm32 r3, 0x46a67717; | |
| imm32 r4, 0x567a891b; | |
| imm32 r5, 0x6789ab1d; | |
| imm32 r6, 0x74445a15; | |
| imm32 r7, 0x866677a7; | |
| R0.L = R1.L + R0.L (NS); | |
| R1.L = R1.L + R1.H (NS); | |
| R2.L = R1.H + R2.L (NS); | |
| R3.L = R1.H + R3.H (NS); | |
| R4.L = R1.L + R4.L (NS); | |
| R5.L = R1.L + R5.H (NS); | |
| R6.L = R1.H + R6.L (NS); | |
| R7.L = R1.H + R7.H (NS); | |
| CHECKREG r4, 0x567ADEC1; | |
| CHECKREG r5, 0x6789BD2F; | |
| CHECKREG r6, 0x7444049E; | |
| CHECKREG r7, 0x866630EF; | |
| CHECKREG r4, 0x567ADEC1; | |
| CHECKREG r5, 0x6789BD2F; | |
| CHECKREG r6, 0x7444049E; | |
| CHECKREG r7, 0x866630EF; | |
| imm32 r0, 0x15678911; | |
| imm32 r1, 0x2789ab1d; | |
| imm32 r2, 0x34445515; | |
| imm32 r3, 0x46667717; | |
| imm32 r4, 0x5678891b; | |
| imm32 r5, 0x6789ab1d; | |
| imm32 r6, 0x74445515; | |
| imm32 r7, 0x86667777; | |
| R0.L = R2.L + R0.L (NS); | |
| R1.L = R2.L + R1.H (NS); | |
| R2.L = R2.H + R2.L (NS); | |
| R3.L = R2.H + R3.H (NS); | |
| R4.L = R2.L + R4.L (NS); | |
| R5.L = R2.L + R5.H (NS); | |
| R6.L = R2.H + R6.L (NS); | |
| R7.L = R2.H + R7.H (NS); | |
| CHECKREG r4, 0x56781274; | |
| CHECKREG r5, 0x6789F0E2; | |
| CHECKREG r6, 0x74448959; | |
| CHECKREG r7, 0x8666BAAA; | |
| CHECKREG r4, 0x56781274; | |
| CHECKREG r5, 0x6789F0E2; | |
| CHECKREG r6, 0x74448959; | |
| CHECKREG r7, 0x8666BAAA; | |
| imm32 r0, 0xb5678911; | |
| imm32 r1, 0x2789ab1d; | |
| imm32 r2, 0x3bb45515; | |
| imm32 r3, 0x46667717; | |
| imm32 r4, 0x567b891b; | |
| imm32 r5, 0x6789ab1d; | |
| imm32 r6, 0x7444b515; | |
| imm32 r7, 0x86667b77; | |
| R0.L = R3.L + R0.L (NS); | |
| R1.L = R3.L + R1.H (NS); | |
| R2.L = R3.H + R2.L (NS); | |
| R3.L = R3.H + R3.H (NS); | |
| R4.L = R3.L + R4.L (NS); | |
| R5.L = R3.L + R5.H (NS); | |
| R6.L = R3.H + R6.L (NS); | |
| R7.L = R3.H + R7.H (NS); | |
| CHECKREG r4, 0x567B15E7; | |
| CHECKREG r5, 0x6789F455; | |
| CHECKREG r6, 0x7444FB7B; | |
| CHECKREG r7, 0x8666CCCC; | |
| CHECKREG r4, 0x567B15E7; | |
| CHECKREG r5, 0x6789F455; | |
| CHECKREG r6, 0x7444FB7B; | |
| CHECKREG r7, 0x8666CCCC; | |
| imm32 r0, 0x15678911; | |
| imm32 r1, 0x2789ab1d; | |
| imm32 r2, 0x34445515; | |
| imm32 r3, 0x46667717; | |
| imm32 r4, 0x5678891b; | |
| imm32 r5, 0x6789ab1d; | |
| imm32 r6, 0x74445515; | |
| imm32 r7, 0x86667777; | |
| R0.L = R4.L + R0.L (NS); | |
| R1.L = R4.L + R1.H (NS); | |
| R2.L = R4.H + R2.L (NS); | |
| R3.L = R4.H + R3.H (NS); | |
| R4.L = R4.L + R4.L (NS); | |
| R5.L = R4.L + R5.H (NS); | |
| R6.L = R4.H + R6.L (NS); | |
| R7.L = R4.H + R7.H (NS); | |
| CHECKREG r4, 0x56781236; | |
| CHECKREG r5, 0x678979BF; | |
| CHECKREG r6, 0x7444AB8D; | |
| CHECKREG r7, 0x8666DCDE; | |
| CHECKREG r4, 0x56781236; | |
| CHECKREG r5, 0x678979BF; | |
| CHECKREG r6, 0x7444AB8D; | |
| CHECKREG r7, 0x8666DCDE; | |
| imm32 r0, 0xcc678911; | |
| imm32 r1, 0x2789ab1d; | |
| imm32 r2, 0x3c445515; | |
| imm32 r3, 0x46c67717; | |
| imm32 r4, 0x567c891b; | |
| imm32 r5, 0x6789cb1d; | |
| imm32 r6, 0x74445515; | |
| imm32 r7, 0x86667c77; | |
| R0.L = R5.L + R0.L (NS); | |
| R1.L = R5.L + R1.H (NS); | |
| R2.L = R5.H + R2.L (NS); | |
| R3.L = R5.H + R3.H (NS); | |
| R4.L = R5.L + R4.L (NS); | |
| R5.L = R5.L + R5.H (NS); | |
| R6.L = R5.H + R6.L (NS); | |
| R7.L = R5.H + R7.H (NS); | |
| CHECKREG r4, 0x567C5438; | |
| CHECKREG r5, 0x678932A6; | |
| CHECKREG r6, 0x7444BC9E; | |
| CHECKREG r7, 0x8666EDEF; | |
| CHECKREG r4, 0x567C5438; | |
| CHECKREG r5, 0x678932A6; | |
| CHECKREG r6, 0x7444BC9E; | |
| CHECKREG r7, 0x8666EDEF; | |
| imm32 r0, 0xd5678911; | |
| imm32 r1, 0x2789ab1d; | |
| imm32 r2, 0x3d445515; | |
| imm32 r3, 0x46d67717; | |
| imm32 r4, 0x5678891b; | |
| imm32 r5, 0x678dab1d; | |
| imm32 r6, 0x7444d515; | |
| imm32 r7, 0x86667d77; | |
| R0.L = R6.L + R0.L (NS); | |
| R1.L = R6.L + R1.H (NS); | |
| R2.L = R6.H + R2.L (NS); | |
| R3.L = R6.H + R3.H (NS); | |
| R4.L = R6.L + R4.L (NS); | |
| R5.L = R6.L + R5.H (NS); | |
| R6.L = R6.H + R6.L (NS); | |
| R7.L = R6.H + R7.H (NS); | |
| CHECKREG r4, 0x56785E30; | |
| CHECKREG r5, 0x678D3CA2; | |
| CHECKREG r6, 0x74444959; | |
| CHECKREG r7, 0x8666FAAA; | |
| CHECKREG r4, 0x56785E30; | |
| CHECKREG r5, 0x678D3CA2; | |
| CHECKREG r6, 0x74444959; | |
| CHECKREG r7, 0x8666FAAA; | |
| imm32 r0, 0xf5678911; | |
| imm32 r1, 0x2f89ab1d; | |
| imm32 r2, 0x34f45515; | |
| imm32 r3, 0x466f7717; | |
| imm32 r4, 0x5678f91b; | |
| imm32 r5, 0x6789af1d; | |
| imm32 r6, 0x744455f5; | |
| imm32 r7, 0x8666777f; | |
| R0.L = R7.L + R0.L (NS); | |
| R1.L = R7.L + R1.H (NS); | |
| R2.L = R7.H + R2.L (NS); | |
| R3.L = R7.H + R3.H (NS); | |
| R4.L = R7.L + R4.L (NS); | |
| R5.L = R7.L + R5.H (NS); | |
| R6.L = R7.H + R6.L (NS); | |
| R7.L = R7.H + R7.H (NS); | |
| CHECKREG r4, 0x5678709A; | |
| CHECKREG r5, 0x6789DF08; | |
| CHECKREG r6, 0x7444DC5B; | |
| CHECKREG r7, 0x86660CCC; | |
| CHECKREG r4, 0x5678709A; | |
| CHECKREG r5, 0x6789DF08; | |
| CHECKREG r6, 0x7444DC5B; | |
| CHECKREG r7, 0x86660CCC; | |
| imm32 r0, 0x55678911; | |
| imm32 r1, 0x2589ab1d; | |
| imm32 r2, 0x35545515; | |
| imm32 r3, 0x46d67717; | |
| imm32 r4, 0x5678891b; | |
| imm32 r5, 0x678dab1d; | |
| imm32 r6, 0x7444d515; | |
| imm32 r7, 0x86667d77; | |
| R6.L = R2.L + R3.L (S); | |
| R1.L = R4.L + R5.H (S); | |
| R5.L = R7.H + R2.L (S); | |
| R3.L = R0.H + R0.H (S); | |
| R0.L = R3.L + R4.L (S); | |
| R2.L = R5.L + R7.H (S); | |
| R7.L = R6.H + R7.L (S); | |
| R4.L = R1.H + R6.H (S); | |
| CHECKREG r4, 0x56787FFF; | |
| CHECKREG r5, 0x678DDB7B; | |
| CHECKREG r6, 0x74447FFF; | |
| CHECKREG r7, 0x86667FFF; | |
| CHECKREG r4, 0x56787FFF; | |
| CHECKREG r5, 0x678DDB7B; | |
| CHECKREG r6, 0x74447FFF; | |
| CHECKREG r7, 0x86667FFF; | |
| imm32 r0, 0x15678911; | |
| imm32 r1, 0x2789ab1d; | |
| imm32 r2, 0x34445515; | |
| imm32 r3, 0x46667717; | |
| imm32 r4, 0x5678891b; | |
| imm32 r5, 0x6789ab1d; | |
| imm32 r6, 0x74445515; | |
| imm32 r7, 0x86667777; | |
| R3.L = R4.L + R0.L (S); | |
| R1.L = R6.L + R3.H (S); | |
| R4.L = R3.H + R2.L (S); | |
| R6.L = R7.H + R1.H (S); | |
| R2.L = R5.L + R4.L (S); | |
| R7.L = R2.L + R7.H (S); | |
| R0.L = R1.H + R6.L (S); | |
| R5.L = R0.H + R5.H (S); | |
| CHECKREG r4, 0x56787FFF; | |
| CHECKREG r5, 0x67897CF0; | |
| CHECKREG r6, 0x7444ADEF; | |
| CHECKREG r7, 0x8666B182; | |
| CHECKREG r4, 0x56787FFF; | |
| CHECKREG r5, 0x67897CF0; | |
| CHECKREG r6, 0x7444ADEF; | |
| CHECKREG r7, 0x8666B182; | |
| pass |