| //Original:/testcases/core/c_dsp32shift_signbits_rh/c_dsp32shift_signbits_rh.dsp | |
| // Spec Reference: dsp32shift signbits dregs_hi | |
| # mach: bfin | |
| .include "testutils.inc" | |
| start | |
| imm32 r0, 0xd1000000; | |
| imm32 r1, 0xd2000001; | |
| imm32 r2, 0xd3000002; | |
| imm32 r3, 0xd4000003; | |
| imm32 r4, 0xd5000004; | |
| imm32 r5, 0xd6000005; | |
| imm32 r6, 0xd7000006; | |
| imm32 r7, 0xd8000007; | |
| R0.L = SIGNBITS R0.H; | |
| R1.L = SIGNBITS R0.H; | |
| R2.L = SIGNBITS R0.H; | |
| R3.L = SIGNBITS R0.H; | |
| R4.L = SIGNBITS R0.H; | |
| R5.L = SIGNBITS R0.H; | |
| R6.L = SIGNBITS R0.H; | |
| R7.L = SIGNBITS R0.H; | |
| CHECKREG r0, 0xD1000001; | |
| CHECKREG r1, 0xD2000001; | |
| CHECKREG r2, 0xD3000001; | |
| CHECKREG r3, 0xD4000001; | |
| CHECKREG r4, 0xD5000001; | |
| CHECKREG r5, 0xD6000001; | |
| CHECKREG r6, 0xD7000001; | |
| CHECKREG r7, 0xD8000001; | |
| imm32 r0, 0xe200d001; | |
| imm32 r1, 0xe2000001; | |
| imm32 r2, 0xe200d002; | |
| imm32 r3, 0xe200d003; | |
| imm32 r4, 0xe200d004; | |
| imm32 r5, 0xe200d005; | |
| imm32 r6, 0xe200d006; | |
| imm32 r7, 0xe200d007; | |
| R0.L = SIGNBITS R1.H; | |
| R1.L = SIGNBITS R1.H; | |
| R2.L = SIGNBITS R1.H; | |
| R3.L = SIGNBITS R1.H; | |
| R4.L = SIGNBITS R1.H; | |
| R5.L = SIGNBITS R1.H; | |
| R6.L = SIGNBITS R1.H; | |
| R7.L = SIGNBITS R1.H; | |
| CHECKREG r0, 0xE2000002; | |
| CHECKREG r1, 0xE2000002; | |
| CHECKREG r2, 0xE2000002; | |
| CHECKREG r3, 0xE2000002; | |
| CHECKREG r4, 0xE2000002; | |
| CHECKREG r5, 0xE2000002; | |
| CHECKREG r6, 0xE2000002; | |
| CHECKREG r7, 0xE2000002; | |
| imm32 r0, 0x0000e001; | |
| imm32 r1, 0x0000e001; | |
| imm32 r2, 0xf000000f; | |
| imm32 r3, 0x0000e003; | |
| imm32 r4, 0x0000e004; | |
| imm32 r5, 0x0000e005; | |
| imm32 r6, 0x0000e006; | |
| imm32 r7, 0x0000e007; | |
| R0.L = SIGNBITS R2.H; | |
| R1.L = SIGNBITS R2.H; | |
| R2.L = SIGNBITS R2.H; | |
| R3.L = SIGNBITS R2.H; | |
| R4.L = SIGNBITS R2.H; | |
| R5.L = SIGNBITS R2.H; | |
| R6.L = SIGNBITS R2.H; | |
| R7.L = SIGNBITS R2.H; | |
| CHECKREG r0, 0x00000003; | |
| CHECKREG r1, 0x00000003; | |
| CHECKREG r2, 0xF0000003; | |
| CHECKREG r3, 0x00000003; | |
| CHECKREG r4, 0x00000003; | |
| CHECKREG r5, 0x00000003; | |
| CHECKREG r6, 0x00000003; | |
| CHECKREG r7, 0x00000003; | |
| imm32 r0, 0x0100f001; | |
| imm32 r1, 0x0100f001; | |
| imm32 r2, 0x0100f002; | |
| imm32 r3, 0x01000010; | |
| imm32 r4, 0x0100f004; | |
| imm32 r5, 0x0100f005; | |
| imm32 r6, 0x0100f006; | |
| imm32 r7, 0x0100f007; | |
| R0.L = SIGNBITS R3.H; | |
| R1.L = SIGNBITS R3.H; | |
| R2.L = SIGNBITS R3.H; | |
| R3.L = SIGNBITS R3.H; | |
| R4.L = SIGNBITS R3.H; | |
| R5.L = SIGNBITS R3.H; | |
| R6.L = SIGNBITS R3.H; | |
| R7.L = SIGNBITS R3.H; | |
| CHECKREG r0, 0x01000006; | |
| CHECKREG r1, 0x01000006; | |
| CHECKREG r2, 0x01000006; | |
| CHECKREG r3, 0x01000006; | |
| CHECKREG r4, 0x01000006; | |
| CHECKREG r5, 0x01000006; | |
| CHECKREG r6, 0x01000006; | |
| CHECKREG r7, 0x01000006; | |
| imm32 r0, 0x04000000; | |
| imm32 r1, 0x04010000; | |
| imm32 r2, 0x04020000; | |
| imm32 r3, 0x04030000; | |
| imm32 r4, 0x04040000; | |
| imm32 r5, 0x04050000; | |
| imm32 r6, 0x04060000; | |
| imm32 r7, 0x04070000; | |
| R0.L = SIGNBITS R4.H; | |
| R1.L = SIGNBITS R4.H; | |
| R2.L = SIGNBITS R4.H; | |
| R3.L = SIGNBITS R4.H; | |
| R4.L = SIGNBITS R4.H; | |
| R5.L = SIGNBITS R4.H; | |
| R6.L = SIGNBITS R4.H; | |
| R7.L = SIGNBITS R4.H; | |
| CHECKREG r0, 0x04000004; | |
| CHECKREG r1, 0x04010004; | |
| CHECKREG r2, 0x04020004; | |
| CHECKREG r3, 0x04030004; | |
| CHECKREG r4, 0x04040004; | |
| CHECKREG r5, 0x04050004; | |
| CHECKREG r6, 0x04060004; | |
| CHECKREG r7, 0x04070004; | |
| imm32 r0, 0xa5010000; | |
| imm32 r1, 0xa5010001; | |
| imm32 r2, 0xa5020000; | |
| imm32 r3, 0xa5030000; | |
| imm32 r4, 0xa5540000; | |
| imm32 r5, 0xa5550000; | |
| imm32 r6, 0xa5060000; | |
| imm32 r7, 0xa5070000; | |
| R0.L = SIGNBITS R5.H; | |
| R1.L = SIGNBITS R5.H; | |
| R2.L = SIGNBITS R5.H; | |
| R3.L = SIGNBITS R5.H; | |
| R4.L = SIGNBITS R5.H; | |
| R5.L = SIGNBITS R5.H; | |
| R6.L = SIGNBITS R5.H; | |
| R7.L = SIGNBITS R5.H; | |
| CHECKREG r0, 0xA5010000; | |
| CHECKREG r1, 0xA5010000; | |
| CHECKREG r2, 0xA5020000; | |
| CHECKREG r3, 0xA5030000; | |
| CHECKREG r4, 0xA5540000; | |
| CHECKREG r5, 0xA5550000; | |
| CHECKREG r6, 0xA5060000; | |
| CHECKREG r7, 0xA5070000; | |
| imm32 r0, 0xb6010000; | |
| imm32 r1, 0xb6010000; | |
| imm32 r2, 0xb602000f; | |
| imm32 r3, 0xb6030000; | |
| imm32 r4, 0xb6040000; | |
| imm32 r5, 0xb6050000; | |
| imm32 r6, 0xb6060000; | |
| imm32 r7, 0xb6670000; | |
| R0.L = SIGNBITS R6.H; | |
| R1.L = SIGNBITS R6.H; | |
| R2.L = SIGNBITS R6.H; | |
| R3.L = SIGNBITS R6.H; | |
| R4.L = SIGNBITS R6.H; | |
| R5.L = SIGNBITS R6.H; | |
| R6.L = SIGNBITS R6.H; | |
| R7.L = SIGNBITS R6.H; | |
| CHECKREG r0, 0xB6010000; | |
| CHECKREG r1, 0xB6010000; | |
| CHECKREG r2, 0xB6020000; | |
| CHECKREG r3, 0xB6030000; | |
| CHECKREG r4, 0xB6040000; | |
| CHECKREG r5, 0xB6050000; | |
| CHECKREG r6, 0xB6060000; | |
| CHECKREG r7, 0xB6670000; | |
| imm32 r0, 0xd7010000; | |
| imm32 r1, 0xd7010000; | |
| imm32 r2, 0xd7020000; | |
| imm32 r3, 0xd7030010; | |
| imm32 r4, 0xd7040000; | |
| imm32 r5, 0xd7050000; | |
| imm32 r6, 0xd7060000; | |
| imm32 r7, 0xd7070000; | |
| R0.L = SIGNBITS R7.H; | |
| R1.L = SIGNBITS R7.H; | |
| R2.L = SIGNBITS R7.H; | |
| R3.L = SIGNBITS R7.H; | |
| R4.L = SIGNBITS R7.H; | |
| R5.L = SIGNBITS R7.H; | |
| R6.L = SIGNBITS R7.H; | |
| R7.L = SIGNBITS R7.H; | |
| CHECKREG r0, 0xD7010001; | |
| CHECKREG r1, 0xD7010001; | |
| CHECKREG r2, 0xD7020001; | |
| CHECKREG r3, 0xD7030001; | |
| CHECKREG r4, 0xD7040001; | |
| CHECKREG r5, 0xD7050001; | |
| CHECKREG r6, 0xD7060001; | |
| CHECKREG r7, 0xD7070001; | |
| pass |