sim/testsuite/bfin/c_regmv_pr_imlb.s

//Original:/testcases/core/c_regmv_pr_imlb/c_regmv_pr_imlb.dsp
// Spec Reference: regmv preg-to-imlb reg
# mach: bfin

.include "testutils.inc"
	start

// check R-reg to imlb-reg move

imm32 r0, 0x00000001;
imm32 p1, 0x00020003;
imm32 p2, 0x00040005;
imm32 p3, 0x00060007;
imm32 p4, 0x00080009;
imm32 p5, 0x000a000b;
imm32 sp, 0x000c000d;
imm32 fp, 0x000e000f;
I0 = P1;
I1 = P1;
I2 = P1;
I3 = P1;
M0 = P1;
M1 = P1;
M2 = P1;
M3 = P1;
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
R4 = M0;
R5 = M1;
R6 = M2;
R7 = M3;
CHECKREG r0, 0x00020003;
CHECKREG r1, 0x00020003;
CHECKREG r2, 0x00020003;
CHECKREG r3, 0x00020003;
CHECKREG r4, 0x00020003;
CHECKREG r5, 0x00020003;
CHECKREG r6, 0x00020003;
CHECKREG r7, 0x00020003;

imm32 p2, 0x00040005;
I0 = P2;
I1 = P2;
I2 = P2;
I3 = P2;
M0 = P2;
M1 = P2;
M2 = P2;
M3 = P2;
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
R4 = M0;
R5 = M1;
R6 = M2;
R7 = M3;
CHECKREG r0, 0x00040005;
CHECKREG r1, 0x00040005;
CHECKREG r2, 0x00040005;
CHECKREG r3, 0x00040005;
CHECKREG r4, 0x00040005;
CHECKREG r5, 0x00040005;
CHECKREG r6, 0x00040005;
CHECKREG r7, 0x00040005;

imm32 p3, 0x00060007;
I0 = P3;
I1 = P3;
I2 = P3;
I3 = P3;
M0 = P3;
M1 = P3;
M2 = P3;
M3 = P3;
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
R4 = M0;
R5 = M1;
R6 = M2;
R7 = M3;
CHECKREG r0, 0x00060007;
CHECKREG r1, 0x00060007;
CHECKREG r2, 0x00060007;
CHECKREG r3, 0x00060007;
CHECKREG r4, 0x00060007;
CHECKREG r5, 0x00060007;
CHECKREG r6, 0x00060007;
CHECKREG r7, 0x00060007;

imm32 p4, 0x00080009;
I0 = P4;
I1 = P4;
I2 = P4;
I3 = P4;
M0 = P4;
M1 = P4;
M2 = P4;
M3 = P4;
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
R4 = M0;
R5 = M1;
R6 = M2;
R7 = M3;
CHECKREG r0, 0x00080009;
CHECKREG r1, 0x00080009;
CHECKREG r2, 0x00080009;
CHECKREG r3, 0x00080009;
CHECKREG r4, 0x00080009;
CHECKREG r5, 0x00080009;
CHECKREG r6, 0x00080009;
CHECKREG r7, 0x00080009;

imm32 p5, 0x000a000b;
I0 = P5;
I1 = P5;
I2 = P5;
I3 = P5;
M0 = P5;
M1 = P5;
M2 = P5;
M3 = P5;
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
R4 = M0;
R5 = M1;
R6 = M2;
R7 = M3;
CHECKREG r0, 0x000a000b;
CHECKREG r1, 0x000a000b;
CHECKREG r2, 0x000a000b;
CHECKREG r3, 0x000a000b;
CHECKREG r4, 0x000a000b;
CHECKREG r5, 0x000a000b;
CHECKREG r6, 0x000a000b;
CHECKREG r7, 0x000a000b;

imm32 sp, 0x000c000d;
I0 = SP;
I1 = SP;
I2 = SP;
I3 = SP;
M0 = SP;
M1 = SP;
M2 = SP;
M3 = SP;
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
R4 = M0;
R5 = M1;
R6 = M2;
R7 = M3;
CHECKREG r0, 0x000c000d;
CHECKREG r1, 0x000c000d;
CHECKREG r2, 0x000c000d;
CHECKREG r3, 0x000c000d;
CHECKREG r4, 0x000c000d;
CHECKREG r5, 0x000c000d;
CHECKREG r6, 0x000c000d;
CHECKREG r7, 0x000c000d;

imm32 fp, 0x000e000f;
I0 = FP;
I1 = FP;
I2 = FP;
I3 = FP;
M0 = FP;
M1 = FP;
M2 = FP;
M3 = FP;
R0 = I0;
R1 = I1;
R2 = I2;
R3 = I3;
R4 = M0;
R5 = M1;
R6 = M2;
R7 = M3;
CHECKREG r0, 0x000e000f;
CHECKREG r1, 0x000e000f;
CHECKREG r2, 0x000e000f;
CHECKREG r3, 0x000e000f;
CHECKREG r4, 0x000e000f;
CHECKREG r5, 0x000e000f;
CHECKREG r6, 0x000e000f;
CHECKREG r7, 0x000e000f;


imm32 p1, 0x00020003;
L0 = P1;
L1 = P1;
L2 = P1;
L3 = P1;
B0 = P1;
B1 = P1;
B2 = P1;
B3 = P1;
R0 = L0;
R1 = L1;
R2 = L2;
R3 = L3;
R4 = B0;
R5 = B1;
R6 = B2;
R7 = B3;
CHECKREG r0, 0x00020003;
CHECKREG r1, 0x00020003;
CHECKREG r2, 0x00020003;
CHECKREG r3, 0x00020003;
CHECKREG r4, 0x00020003;
CHECKREG r5, 0x00020003;
CHECKREG r6, 0x00020003;
CHECKREG r7, 0x00020003;

imm32 p2, 0x00040005;
L0 = P2;
L1 = P2;
L2 = P2;
L3 = P2;
B0 = P2;
B1 = P2;
B2 = P2;
B3 = P2;
R0 = L0;
R1 = L1;
R2 = L2;
R3 = L3;
R4 = B0;
R5 = B1;
R6 = B2;
R7 = B3;
CHECKREG r0, 0x00040005;
CHECKREG r1, 0x00040005;
CHECKREG r2, 0x00040005;
CHECKREG r3, 0x00040005;
CHECKREG r4, 0x00040005;
CHECKREG r5, 0x00040005;
CHECKREG r6, 0x00040005;
CHECKREG r7, 0x00040005;

imm32 p3, 0x00060007;
L0 = P3;
L1 = P3;
L2 = P3;
L3 = P3;
B0 = P3;
B1 = P3;
B2 = P3;
B3 = P3;
R0 = L0;
R1 = L1;
R2 = L2;
R3 = L3;
R4 = B0;
R5 = B1;
R6 = B2;
R7 = B3;
CHECKREG r0, 0x00060007;
CHECKREG r1, 0x00060007;
CHECKREG r2, 0x00060007;
CHECKREG r3, 0x00060007;
CHECKREG r4, 0x00060007;
CHECKREG r5, 0x00060007;
CHECKREG r6, 0x00060007;
CHECKREG r7, 0x00060007;

imm32 p4, 0x00080009;
L0 = P4;
L1 = P4;
L2 = P4;
L3 = P4;
B0 = P4;
B1 = P4;
B2 = P4;
B3 = P4;
R0 = L0;
R1 = L1;
R2 = L2;
R3 = L3;
R4 = B0;
R5 = B1;
R6 = B2;
R7 = B3;
CHECKREG r0, 0x00080009;
CHECKREG r1, 0x00080009;
CHECKREG r2, 0x00080009;
CHECKREG r3, 0x00080009;
CHECKREG r4, 0x00080009;
CHECKREG r5, 0x00080009;
CHECKREG r6, 0x00080009;
CHECKREG r7, 0x00080009;

imm32 p5, 0x000a000b;
L0 = P5;
L1 = P5;
L2 = P5;
L3 = P5;
B0 = P5;
B1 = P5;
B2 = P5;
B3 = P5;
R0 = L0;
R1 = L1;
R2 = L2;
R3 = L3;
R4 = B0;
R5 = B1;
R6 = B2;
R7 = B3;
CHECKREG r0, 0x000a000b;
CHECKREG r1, 0x000a000b;
CHECKREG r2, 0x000a000b;
CHECKREG r3, 0x000a000b;
CHECKREG r4, 0x000a000b;
CHECKREG r5, 0x000a000b;
CHECKREG r6, 0x000a000b;
CHECKREG r7, 0x000a000b;

imm32 sp, 0x000c000d;
L0 = SP;
L1 = SP;
L2 = SP;
L3 = SP;
B0 = SP;
B1 = SP;
B2 = SP;
B3 = SP;
R0 = L0;
R1 = L1;
R2 = L2;
R3 = L3;
R4 = B0;
R5 = B1;
R6 = B2;
R7 = B3;
CHECKREG r0, 0x000c000d;
CHECKREG r1, 0x000c000d;
CHECKREG r2, 0x000c000d;
CHECKREG r3, 0x000c000d;
CHECKREG r4, 0x000c000d;
CHECKREG r5, 0x000c000d;
CHECKREG r6, 0x000c000d;
CHECKREG r7, 0x000c000d;

imm32 fp, 0x000e000f;
L0 = FP;
L1 = FP;
L2 = FP;
L3 = FP;
B0 = FP;
B1 = FP;
B2 = FP;
B3 = FP;
R0 = L0;
R1 = L1;
R2 = L2;
R3 = L3;
R4 = B0;
R5 = B1;
R6 = B2;
R7 = B3;
CHECKREG r0, 0x000e000f;
CHECKREG r1, 0x000e000f;
CHECKREG r2, 0x000e000f;
CHECKREG r3, 0x000e000f;
CHECKREG r4, 0x000e000f;
CHECKREG r5, 0x000e000f;
CHECKREG r6, 0x000e000f;
CHECKREG r7, 0x000e000f;

pass