| # frv testcase for csubcc $GRi,$GRj,$GRk,$CCi,$cond |
| # mach: all |
| |
| .include "testutils.inc" |
| |
| start |
| |
| .global csubcc |
| csubcc: |
| set_spr_immed 0x1b1b,cccr |
| |
| set_gr_immed 1,gr7 |
| set_gr_immed 2,gr8 |
| set_icc 0x0f,0 ; Set mask opposite of expected |
| csubcc gr8,gr7,gr8,cc0,1 |
| test_icc 0 0 0 0 icc0 |
| test_gr_immed 1,gr8 |
| |
| set_gr_immed 1,gr7 |
| set_gr_limmed 0x8000,0x0000,gr8 |
| set_icc 0x0d,0 ; Set mask opposite of expected |
| csubcc gr8,gr7,gr8,cc0,1 |
| test_icc 0 0 1 0 icc0 |
| test_gr_limmed 0x7fff,0xffff,gr8 |
| |
| set_icc 0x0b,0 ; Set mask opposite of expected |
| csubcc gr8,gr8,gr8,cc4,1 |
| test_icc 0 1 0 0 icc0 |
| test_gr_immed 0,gr8 |
| |
| set_icc 0x06,0 ; Set mask opposite of expected |
| csubcc gr8,gr7,gr8,cc4,1 |
| test_icc 1 0 0 1 icc0 |
| test_gr_limmed 0xffff,0xffff,gr8 |
| |
| set_gr_immed 1,gr7 |
| set_gr_immed 2,gr8 |
| set_icc 0x0f,0 ; Set mask opposite of expected |
| csubcc gr8,gr7,gr8,cc0,0 |
| test_icc 1 1 1 1 icc0 |
| test_gr_immed 2,gr8 |
| |
| set_gr_immed 1,gr7 |
| set_gr_limmed 0x8000,0x0000,gr8 |
| set_icc 0x0d,0 ; Set mask opposite of expected |
| csubcc gr8,gr7,gr8,cc0,0 |
| test_icc 1 1 0 1 icc0 |
| test_gr_limmed 0x8000,0x0000,gr8 |
| |
| set_icc 0x0b,0 ; Set mask opposite of expected |
| csubcc gr8,gr8,gr8,cc4,0 |
| test_icc 1 0 1 1 icc0 |
| test_gr_limmed 0x8000,0x0000,gr8 |
| |
| set_icc 0x06,0 ; Set mask opposite of expected |
| csubcc gr8,gr7,gr8,cc4,0 |
| test_icc 0 1 1 0 icc0 |
| test_gr_limmed 0x8000,0x0000,gr8 |
| |
| set_gr_immed 1,gr7 |
| set_gr_immed 2,gr8 |
| set_icc 0x0f,1 ; Set mask opposite of expected |
| csubcc gr8,gr7,gr8,cc1,0 |
| test_icc 0 0 0 0 icc1 |
| test_gr_immed 1,gr8 |
| |
| set_gr_immed 1,gr7 |
| set_gr_limmed 0x8000,0x0000,gr8 |
| set_icc 0x0d,1 ; Set mask opposite of expected |
| csubcc gr8,gr7,gr8,cc1,0 |
| test_icc 0 0 1 0 icc1 |
| test_gr_limmed 0x7fff,0xffff,gr8 |
| |
| set_icc 0x0b,1 ; Set mask opposite of expected |
| csubcc gr8,gr8,gr8,cc5,0 |
| test_icc 0 1 0 0 icc1 |
| test_gr_immed 0,gr8 |
| |
| set_icc 0x06,1 ; Set mask opposite of expected |
| csubcc gr8,gr7,gr8,cc5,0 |
| test_icc 1 0 0 1 icc1 |
| test_gr_limmed 0xffff,0xffff,gr8 |
| |
| set_gr_immed 1,gr7 |
| set_gr_immed 2,gr8 |
| set_icc 0x0f,1 ; Set mask opposite of expected |
| csubcc gr8,gr7,gr8,cc1,1 |
| test_icc 1 1 1 1 icc1 |
| test_gr_immed 2,gr8 |
| |
| set_gr_immed 1,gr7 |
| set_gr_limmed 0x8000,0x0000,gr8 |
| set_icc 0x0d,1 ; Set mask opposite of expected |
| csubcc gr8,gr7,gr8,cc1,1 |
| test_icc 1 1 0 1 icc1 |
| test_gr_limmed 0x8000,0x0000,gr8 |
| |
| set_icc 0x0b,1 ; Set mask opposite of expected |
| csubcc gr8,gr8,gr8,cc5,1 |
| test_icc 1 0 1 1 icc1 |
| test_gr_limmed 0x8000,0x0000,gr8 |
| |
| set_icc 0x06,1 ; Set mask opposite of expected |
| csubcc gr8,gr7,gr8,cc5,1 |
| test_icc 0 1 1 0 icc1 |
| test_gr_limmed 0x8000,0x0000,gr8 |
| |
| set_gr_immed 1,gr7 |
| set_gr_immed 2,gr8 |
| set_icc 0x0f,2 ; Set mask opposite of expected |
| csubcc gr8,gr7,gr8,cc2,0 |
| test_icc 1 1 1 1 icc2 |
| test_gr_immed 2,gr8 |
| |
| set_gr_immed 1,gr7 |
| set_gr_limmed 0x8000,0x0000,gr8 |
| set_icc 0x0d,2 ; Set mask opposite of expected |
| csubcc gr8,gr7,gr8,cc2,0 |
| test_icc 1 1 0 1 icc2 |
| test_gr_limmed 0x8000,0x0000,gr8 |
| |
| set_icc 0x0b,2 ; Set mask opposite of expected |
| csubcc gr8,gr8,gr8,cc6,1 |
| test_icc 1 0 1 1 icc2 |
| test_gr_limmed 0x8000,0x0000,gr8 |
| |
| set_icc 0x06,2 ; Set mask opposite of expected |
| csubcc gr8,gr7,gr8,cc6,1 |
| test_icc 0 1 1 0 icc2 |
| test_gr_limmed 0x8000,0x0000,gr8 |
| |
| set_gr_immed 1,gr7 |
| set_gr_immed 2,gr8 |
| set_icc 0x0f,3 ; Set mask opposite of expected |
| csubcc gr8,gr7,gr8,cc3,0 |
| test_icc 1 1 1 1 icc3 |
| test_gr_immed 2,gr8 |
| |
| set_gr_immed 1,gr7 |
| set_gr_limmed 0x8000,0x0000,gr8 |
| set_icc 0x0d,3 ; Set mask opposite of expected |
| csubcc gr8,gr7,gr8,cc3,0 |
| test_icc 1 1 0 1 icc3 |
| test_gr_limmed 0x8000,0x0000,gr8 |
| |
| set_icc 0x0b,3 ; Set mask opposite of expected |
| csubcc gr8,gr8,gr8,cc7,1 |
| test_icc 1 0 1 1 icc3 |
| test_gr_limmed 0x8000,0x0000,gr8 |
| |
| set_icc 0x06,3 ; Set mask opposite of expected |
| csubcc gr8,gr7,gr8,cc7,1 |
| test_icc 0 1 1 0 icc3 |
| test_gr_limmed 0x8000,0x0000,gr8 |
| |
| pass |
