)]}'
{
  "commit": "762c38d552abbfed97c349c5e7c8ef34119b2f5e",
  "tree": "f0b1d2e5cf0b78204d6ab4d0f8c7dd8c9512a5b7",
  "parents": [
    "479edf0a6a61159486f14d5e62403f8769cc591d"
  ],
  "author": {
    "name": "Yixuan Chen",
    "email": "chenyixuan@iscas.ac.cn",
    "time": "Thu Jul 04 17:16:59 2024 +0800"
  },
  "committer": {
    "name": "Vladimir Mezentsev",
    "email": "vladimir.mezentsev@oracle.com",
    "time": "Wed Jul 10 15:16:03 2024 -0700"
  },
  "message": "RISC-V:[gprofng] Minimal support gprofng for riscv.\n\nChangeLog: Add target riscv to --enable-gprofng.\n\n2024-07-04  Yixuan Chen  \u003cchenyixuan@iscas.ac.cn\u003e\n\n        * configure: Add riscv.\n        * configure.ac: Add riscv.\n\ngprofng/ChangeLog: Minimal support gprofng for riscv.\n\n2024-07-04  Yixuan Chen  \u003cchenyixuan@iscas.ac.cn\u003e\n\n        * gprofng/common/core_pcbe.c (core_pcbe_init): Add RISC-V vendor conditon.\n        (defined): Add riscv.\n        * gprofng/common/cpuid.c (defined): Add risc-v hwprobe.\n        * gprofng/common/gp-defs.h (TOK_A_RISCV): Add riscv.\n        (defined): Add riscv.\n        (ARCH_RISCV): Add riscv.\n        * gprofng/common/hwc_cpus.h: Add RISC-V vendor.\n        * gprofng/common/hwcfuncs.h (HW_INTERVAL_TYPE): Remove useless defination.\n        * gprofng/configure: Add riscv.\n        * gprofng/configure.ac: Add riscv.\n        * gprofng/libcollector/hwprofile.h (ARCH): Add RISC-V register.\n        (CONTEXT_PC): Add RISC-V register.\n        (CONTEXT_FP): Add RISC-V register.\n        (CONTEXT_SP): Add RISC-V register.\n        (SETFUNCTIONCONTEXT):\n        * gprofng/libcollector/libcol_util.c (__collector_util_init): Fix libc open condition.\n        * gprofng/libcollector/libcol_util.h (ARCH): Add RISC-V.\n        * gprofng/libcollector/unwind.c (ARCH): Add RISC-V register.\n        (GET_PC): Add RISC-V register.\n        (GET_SP): Add RISC-V register.\n        (GET_FP): Add RISC-V register.\n        (FILL_CONTEXT):\n        * gprofng/src/DbeSession.cc (ARCH): Add RISC-V.\n        * gprofng/src/Disasm.cc (Disasm::disasm_open): Add RISC-V.\n        * gprofng/src/Experiment.cc (Experiment::ExperimentHandler::startElement): Add RISC-V.\n        * gprofng/src/checks.cc (ARCH): Add RISC-V.\n        * gprofng/src/collctrl.cc (defined): Set risc-v cpu frequency to 1000MHz as default for now, will fix when I find a better method to get cpu frequency.\n        (read_cpuinfo): Add \"mvendorid\" condition according to risc-v /proc/cpuinfo file content.\n        * gprofng/src/dbe_types.h (enum Platform_t): Add RISC-V.\n",
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