| # frv testcase for bcltlr $ICCi,$ccond,$hint | |
| # mach: all | |
| .include "testutils.inc" | |
| start | |
| .global bcltlr | |
| bcltlr: | |
| ; ccond is true | |
| set_spr_immed 128,lcr | |
| set_spr_addr bad,lr | |
| set_icc 0x0 0 | |
| bcltlr icc0,0,0 | |
| set_spr_addr bad,lr | |
| set_icc 0x1 1 | |
| bcltlr icc1,0,1 | |
| set_spr_addr ok3,lr | |
| set_icc 0x2 2 | |
| bcltlr icc2,0,2 | |
| fail | |
| ok3: | |
| set_spr_addr ok4,lr | |
| set_icc 0x3 3 | |
| bcltlr icc3,0,3 | |
| fail | |
| ok4: | |
| set_spr_addr bad,lr | |
| set_icc 0x4 0 | |
| bcltlr icc0,0,0 | |
| set_spr_addr bad,lr | |
| set_icc 0x5 1 | |
| bcltlr icc1,0,1 | |
| set_spr_addr ok7,lr | |
| set_icc 0x6 2 | |
| bcltlr icc2,0,2 | |
| fail | |
| ok7: | |
| set_spr_addr ok8,lr | |
| set_icc 0x7 3 | |
| bcltlr icc3,0,3 | |
| fail | |
| ok8: | |
| set_spr_addr ok9,lr | |
| set_icc 0x8 0 | |
| bcltlr icc0,0,0 | |
| fail | |
| ok9: | |
| set_spr_addr oka,lr | |
| set_icc 0x9 1 | |
| bcltlr icc1,0,1 | |
| fail | |
| oka: | |
| set_spr_addr bad,lr | |
| set_icc 0xa 2 | |
| bcltlr icc2,0,2 | |
| set_spr_addr bad,lr | |
| set_icc 0xb 3 | |
| bcltlr icc3,0,3 | |
| set_spr_addr okd,lr | |
| set_icc 0xc 0 | |
| bcltlr icc0,0,0 | |
| fail | |
| okd: | |
| set_spr_addr oke,lr | |
| set_icc 0xd 1 | |
| bcltlr icc1,0,1 | |
| fail | |
| oke: | |
| set_spr_addr bad,lr | |
| set_icc 0xe 2 | |
| bcltlr icc2,0,2 | |
| set_spr_addr bad,lr | |
| set_icc 0xf 3 | |
| bcltlr icc3,0,3 | |
| ; ccond is true | |
| set_spr_immed 1,lcr | |
| set_spr_addr bad,lr | |
| set_icc 0x0 0 | |
| bcltlr icc0,1,0 | |
| set_spr_immed 1,lcr | |
| set_spr_addr bad,lr | |
| set_icc 0x1 1 | |
| bcltlr icc1,1,1 | |
| set_spr_immed 1,lcr | |
| set_spr_addr okj,lr | |
| set_icc 0x2 2 | |
| bcltlr icc2,1,2 | |
| fail | |
| okj: | |
| set_spr_immed 1,lcr | |
| set_spr_addr okk,lr | |
| set_icc 0x3 3 | |
| bcltlr icc3,1,3 | |
| fail | |
| okk: | |
| set_spr_immed 1,lcr | |
| set_spr_addr bad,lr | |
| set_icc 0x4 0 | |
| bcltlr icc0,1,0 | |
| set_spr_immed 1,lcr | |
| set_spr_addr bad,lr | |
| set_icc 0x5 1 | |
| bcltlr icc1,1,1 | |
| set_spr_immed 1,lcr | |
| set_spr_addr okn,lr | |
| set_icc 0x6 2 | |
| bcltlr icc2,1,2 | |
| fail | |
| okn: | |
| set_spr_immed 1,lcr | |
| set_spr_addr oko,lr | |
| set_icc 0x7 3 | |
| bcltlr icc3,1,3 | |
| fail | |
| oko: | |
| set_spr_immed 1,lcr | |
| set_spr_addr okp,lr | |
| set_icc 0x8 0 | |
| bcltlr icc0,1,0 | |
| fail | |
| okp: | |
| set_spr_immed 1,lcr | |
| set_spr_addr okq,lr | |
| set_icc 0x9 1 | |
| bcltlr icc1,1,1 | |
| fail | |
| okq: | |
| set_spr_immed 1,lcr | |
| set_spr_addr bad,lr | |
| set_icc 0xa 2 | |
| bcltlr icc2,1,2 | |
| set_spr_immed 1,lcr | |
| set_spr_addr bad,lr | |
| set_icc 0xb 3 | |
| bcltlr icc3,1,3 | |
| set_spr_immed 1,lcr | |
| set_spr_addr okt,lr | |
| set_icc 0xc 0 | |
| bcltlr icc0,1,0 | |
| fail | |
| okt: | |
| set_spr_immed 1,lcr | |
| set_spr_addr oku,lr | |
| set_icc 0xd 1 | |
| bcltlr icc1,1,1 | |
| fail | |
| oku: | |
| set_spr_immed 1,lcr | |
| set_spr_addr bad,lr | |
| set_icc 0xe 2 | |
| bcltlr icc2,1,2 | |
| set_spr_immed 1,lcr | |
| set_spr_addr bad,lr | |
| set_icc 0xf 3 | |
| bcltlr icc3,1,3 | |
| ; ccond is false | |
| set_spr_immed 128,lcr | |
| set_spr_addr bad,lr | |
| set_icc 0x0 0 | |
| bcltlr icc0,1,0 | |
| set_icc 0x1 1 | |
| bcltlr icc1,1,1 | |
| set_icc 0x2 2 | |
| bcltlr icc2,1,2 | |
| set_icc 0x3 3 | |
| bcltlr icc3,1,3 | |
| set_icc 0x4 0 | |
| bcltlr icc0,1,0 | |
| set_icc 0x5 1 | |
| bcltlr icc1,1,1 | |
| set_icc 0x6 2 | |
| bcltlr icc2,1,2 | |
| set_icc 0x7 3 | |
| bcltlr icc3,1,3 | |
| set_icc 0x8 0 | |
| bcltlr icc0,1,0 | |
| set_icc 0x9 1 | |
| bcltlr icc1,1,1 | |
| set_icc 0xa 2 | |
| bcltlr icc2,1,2 | |
| set_icc 0xb 3 | |
| bcltlr icc3,1,3 | |
| set_icc 0xc 0 | |
| bcltlr icc0,1,0 | |
| set_icc 0xd 1 | |
| bcltlr icc1,1,1 | |
| set_icc 0xe 2 | |
| bcltlr icc2,1,2 | |
| set_icc 0xf 3 | |
| bcltlr icc3,1,3 | |
| ; ccond is false | |
| set_spr_immed 1,lcr | |
| set_spr_addr bad,lr | |
| set_icc 0x0 0 | |
| bcltlr icc0,0,0 | |
| set_spr_immed 1,lcr | |
| set_icc 0x1 1 | |
| bcltlr icc1,0,1 | |
| set_spr_immed 1,lcr | |
| set_icc 0x2 2 | |
| bcltlr icc2,0,2 | |
| set_spr_immed 1,lcr | |
| set_icc 0x3 3 | |
| bcltlr icc3,0,3 | |
| set_spr_immed 1,lcr | |
| set_icc 0x4 0 | |
| bcltlr icc0,0,0 | |
| set_spr_immed 1,lcr | |
| set_icc 0x5 1 | |
| bcltlr icc1,0,1 | |
| set_spr_immed 1,lcr | |
| set_icc 0x6 2 | |
| bcltlr icc2,0,2 | |
| set_spr_immed 1,lcr | |
| set_icc 0x7 3 | |
| bcltlr icc3,0,3 | |
| set_spr_immed 1,lcr | |
| set_icc 0x8 0 | |
| bcltlr icc0,0,0 | |
| set_spr_immed 1,lcr | |
| set_icc 0x9 1 | |
| bcltlr icc1,0,1 | |
| set_spr_immed 1,lcr | |
| set_icc 0xa 2 | |
| bcltlr icc2,0,2 | |
| set_spr_immed 1,lcr | |
| set_icc 0xb 3 | |
| bcltlr icc3,0,3 | |
| set_spr_immed 1,lcr | |
| set_icc 0xc 0 | |
| bcltlr icc0,0,0 | |
| set_spr_immed 1,lcr | |
| set_icc 0xd 1 | |
| bcltlr icc1,0,1 | |
| set_spr_immed 1,lcr | |
| set_icc 0xe 2 | |
| bcltlr icc2,0,2 | |
| set_spr_immed 1,lcr | |
| set_icc 0xf 3 | |
| bcltlr icc3,0,3 | |
| pass | |
| bad: | |
| fail |