RISC-V: THEAD: Add 5 assembly pseudoinstructions for XTheadVector extension

In order to make it easier to complete the compiler's support for
the XTheadVector extension and to be as compatible as possible
with the programming model of the 'V' extension ([1]), we consider
adding a few pseudo instructions ([2]).

th.vmmv.m vd,vs		=> th.vmand.mm vd,vs,vs
th.vneg.v vd,vs		=> th.vrsub.vx vd,vs,x0
th.vncvt.x.x.v vd,vs,vm	=> th.vnsrl.vx vd,vs,x0,vm
th.vfneg.v vd,vs	=> th.vfsgnjn.vv vd,vs,vs
th.vfabs.v vd,vs	=> th.vfsgnjx.vv vd,vs,vs

Ref:
[1] https://gcc.gnu.org/pipermail/gcc-patches/2023-December/641302.html
[2] https://github.com/T-head-Semi/thead-extension-spec/pull/40

Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com>
Co-developed-by: Christoph Müllner <christoph.muellner@vrull.eu>

gas/ChangeLog:

	* testsuite/gas/riscv/x-thead-vector.d: Add tests for new
	pseudoinstructions.
	* testsuite/gas/riscv/x-thead-vector.s: Likewise.

opcodes/ChangeLog:

	* riscv-opc.c: Add new pseudoinstructions.