tree 15e08a31ae29b56e4b4e04d464c0e2bae8d76739
parent acf4fe13d46e15a09cb922247bf70157e4ff8656
author Tamar Christina <tamar.christina@arm.com> 1513685053 +0000
committer Adhemerval Zanella <adhemerval.zanella@linaro.org> 1516038250 -0200

Add support for V_4B so we can properly reject it.

Previously parse_vector_type_for_operand was changed to allow the use of 4b
register size for indexed lane instructions. However this had the unintended
side effect of also allowing 4b for normal vector registers.

Because this support was only partial the rest of the tool silently treated
4b as 8b and continued. This patch adds full support for 4b so it can be
properly distinguished from 8b and the correct errors are generated.

With this patch you still can't encode any instruction which actually requires
v<num>.4b but such instructions don't exist so to prevent needing a workaround
in get_vreg_qualifier_from_value this was just omitted.

gas/

	PR gas/22529
	* config/tc-aarch64.c (vectype_to_qualifier): Support AARCH64_OPND_QLF_V_4B.
	* gas/testsuite/gas/aarch64/pr22529.s: New.
	* gas/testsuite/gas/aarch64/pr22529.d: New.
	* gas/testsuite/gas/aarch64/pr22529.l: New.

include/

	PR gas/22529
	* opcode/aarch64.h (aarch64_opnd_qualifier): Add AARCH64_OPND_QLF_V_4B.

opcodes/

	PR gas/22529
	* aarch64-opc.c (aarch64_opnd_qualifiers): Add 4b variant.