commit 81a3befa0ac2ed1e7b2562c1a12d188623c5c3d1
author Mike Frysinger <vapier@gentoo.org> Wed Dec 06 20:08:01 2023 -0700
committer Mike Frysinger <vapier@gentoo.org> Fri Dec 15 21:14:13 2023 -0500
tree 85d33a8cb7dcc20ccb3d240d6c4a6ddc8c16b27e
parent 18054f49ca94b9e9e9d5791abb83ee2967190583

sim: mn10300: fix incorrect implementation of a few insns

Fix a few problems caught by compiler warnings:
* Some of the asr & lsr insns were setting up the c state flag,
  but then forgetting to set it in the PSW.  Add it like the other
  asr & lsr variants.
* Some of the dmulh insns were multiplying one of the source regs
  against itself instead of against the other source reg.
* The sat16_cmp parallel insn was using the wrong register in the
  compare -- the reg1 src/dst pair are used in the sat16 op, and
  the reg2 src/dst pair are used in the add op.

sim/mn10300/am33.igen

diff --git a/sim/mn10300/am33.igen b/sim/mn10300/am33.igen
index da8f88f..a3a40b7 100644
--- a/sim/mn10300/am33.igen
+++ b/sim/mn10300/am33.igen
@@ -2706,7 +2706,7 @@
   n = (State.regs[dstreg] & 0x80000000);
 
   PSW &= ~(PSW_Z | PSW_N | PSW_C);
-  PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
+  PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
 }
 
 // 1111 1011 0101 1101 Rm Rn Rd; lsr Rm,Rn,Rd
@@ -2730,7 +2730,7 @@
   n = (State.regs[dstreg] & 0x80000000);
 
   PSW &= ~(PSW_Z | PSW_N | PSW_C);
-  PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
+  PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
 }
 
 // 1111 1011 0110 1101 Rm Rn Rd; asl Rm,Rn,Rd
@@ -3252,10 +3252,10 @@
   dstreg2 = translate_rreg (SD_, RD2);
 
   temp = ((int32_t)(State.regs[srcreg1] & 0xffff)
-          * (int32_t)(State.regs[srcreg1] & 0xffff));
+          * (int32_t)(State.regs[srcreg2] & 0xffff));
   State.regs[dstreg2] = temp;
   temp = ((int32_t)((State.regs[srcreg1] >> 16) & 0xffff)
-          * (int32_t)((State.regs[srcreg1] >>16) & 0xffff));
+          * (int32_t)((State.regs[srcreg2] >> 16) & 0xffff));
   State.regs[dstreg1] = temp;
 }
 
@@ -3275,10 +3275,10 @@
   dstreg2 = translate_rreg (SD_, RD2);
 
   temp = ((uint32_t)(State.regs[srcreg1] & 0xffff)
-          * (uint32_t)(State.regs[srcreg1] & 0xffff));
+          * (uint32_t)(State.regs[srcreg2] & 0xffff));
   State.regs[dstreg2] = temp;
   temp = ((uint32_t)((State.regs[srcreg1] >> 16) & 0xffff)
-          * (uint32_t)((State.regs[srcreg1] >>16) & 0xffff));
+          * (uint32_t)((State.regs[srcreg2] >> 16) & 0xffff));
   State.regs[dstreg1] = temp;
 }
 
@@ -8646,7 +8646,7 @@
   dstreg1 = translate_rreg (SD_, RN1);
   dstreg2 = translate_rreg (SD_, RN2);
 
-  genericCmp (State.regs[dstreg2], State.regs[dstreg1]);
+  genericCmp (State.regs[srcreg2], State.regs[dstreg2]);
   if (State.regs[srcreg1] >= 0x7fff)
     State.regs[dstreg1] = 0x7fff;
   else if (State.regs[srcreg1] <= 0xffff8000)