)]}'
{
  "commit": "83029f7ff5d571dff0190e8d92c26e032c7acd76",
  "tree": "9284fece401f163d1ba0c721bf2cb27c009fc834",
  "parents": [
    "3190ebcbbf846617c0d5026995c26917f609a0f4"
  ],
  "author": {
    "name": "Tsukasa OI",
    "email": "research_trasio@irq.a4lg.com",
    "time": "Thu Oct 06 04:18:52 2022 +0000"
  },
  "committer": {
    "name": "Tsukasa OI",
    "email": "research_trasio@irq.a4lg.com",
    "time": "Fri Oct 28 14:17:34 2022 +0000"
  },
  "message": "RISC-V: Fallback for instructions longer than 64b\n\nWe don\u0027t support instructions longer than 64-bits yet.  Still, we can\nmodify validate_riscv_insn function to prevent unexpected behavior by\nlimiting the \"length\" of an instruction to 64-bit (or less).\n\ngas/ChangeLog:\n\n\t* config/tc-riscv.c (validate_riscv_insn): Fix function\n\tdescription comment based on current spec.  Limit instruction\n\tlength up to 64-bit for now.  Make sure that required_bits does\n\tnot corrupt even if unsigned long long is longer than 64-bit.\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "01bfc01b0fcab4c89ef710e60d9279a7bff0343d",
      "old_mode": 33188,
      "old_path": "gas/config/tc-riscv.c",
      "new_id": "70558796c24dee44d450cd950b783b169fa52d1b",
      "new_mode": 33188,
      "new_path": "gas/config/tc-riscv.c"
    }
  ]
}