RISC-V: Tidy and aligned riscv_supported_std_[z|x]_ext tables
diff --git a/bfd/elfxx-riscv.c b/bfd/elfxx-riscv.c index 3b92fbe..27d439a 100644 --- a/bfd/elfxx-riscv.c +++ b/bfd/elfxx-riscv.c
@@ -1448,108 +1448,108 @@ static const struct riscv_supported_ext riscv_supported_std_z_ext[] = { - {"zic64b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, - {"ziccamoa", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, - {"ziccif", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, - {"zicclsm", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, - {"ziccrse", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, - {"zicbom", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, - {"zicbop", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, - {"zicboz", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, - {"zicond", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, - {"zicntr", ISA_SPEC_CLASS_DRAFT, 2, 0, 0 }, - {"zicsr", ISA_SPEC_CLASS_20191213, 2, 0, 0 }, - {"zicsr", ISA_SPEC_CLASS_20190608, 2, 0, 0 }, - {"zifencei", ISA_SPEC_CLASS_20191213, 2, 0, 0 }, - {"zifencei", ISA_SPEC_CLASS_20190608, 2, 0, 0 }, - {"zihintntl", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, - {"zihintpause", ISA_SPEC_CLASS_DRAFT, 2, 0, 0 }, - {"zihpm", ISA_SPEC_CLASS_DRAFT, 2, 0, 0 }, - {"zimop", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, - {"zicfiss", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, - {"zicfilp", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, - {"zilsd", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, - {"zmmul", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, - {"za64rs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, - {"za128rs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, - {"zaamo", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, - {"zabha", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, - {"zacas", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, - {"zalrsc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, - {"zawrs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, - {"zfbfmin", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, - {"zfa", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, - {"zfh", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, - {"zfhmin", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, - {"zfinx", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, - {"zdinx", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, - {"zqinx", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, - {"zhinx", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, - {"zhinxmin", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, - {"zbb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, - {"zba", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, - {"zbc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, - {"zbs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, - {"zbkb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, - {"zbkc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, - {"zbkx", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, - {"zk", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, - {"zkn", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, - {"zknd", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, - {"zkne", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, - {"zknh", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, - {"zkr", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, - {"zks", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, - {"zksed", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, - {"zksh", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, - {"zkt", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, - {"zve32x", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, - {"zve32f", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, - {"zve64x", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, - {"zve64f", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, - {"zve64d", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, - {"zvbb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, - {"zvbc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, - {"zvfbfmin", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, - {"zvfbfwma", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, - {"zvfh", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, - {"zvfhmin", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, - {"zvkb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, - {"zvkg", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, - {"zvkn", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, - {"zvkng", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, - {"zvknc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, - {"zvkned", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, - {"zvknha", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, - {"zvknhb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, - {"zvksed", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, - {"zvksh", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, - {"zvks", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, - {"zvksg", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, - {"zvksc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, - {"zvkt", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, - {"zvl32b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, - {"zvl64b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, - {"zvl128b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, - {"zvl256b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, - {"zvl512b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, - {"zvl1024b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, - {"zvl2048b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, - {"zvl4096b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, - {"zvl8192b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, - {"zvl16384b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, - {"zvl32768b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, - {"zvl65536b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, - {"ztso", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, - {"zca", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, - {"zcb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, - {"zce", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, - {"zcf", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, - {"zcd", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, - {"zcmop", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, - {"zcmp", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, - {"zcmt", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, - {"zclsd", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zic64b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"ziccamoa", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"ziccif", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zicclsm", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"ziccrse", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zicbom", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zicbop", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zicboz", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zicond", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zicntr", ISA_SPEC_CLASS_DRAFT, 2, 0, 0 }, + {"zicsr", ISA_SPEC_CLASS_20191213, 2, 0, 0 }, + {"zicsr", ISA_SPEC_CLASS_20190608, 2, 0, 0 }, + {"zifencei", ISA_SPEC_CLASS_20191213, 2, 0, 0 }, + {"zifencei", ISA_SPEC_CLASS_20190608, 2, 0, 0 }, + {"zihintntl", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zihintpause", ISA_SPEC_CLASS_DRAFT, 2, 0, 0 }, + {"zihpm", ISA_SPEC_CLASS_DRAFT, 2, 0, 0 }, + {"zimop", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zicfiss", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zicfilp", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zilsd", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zmmul", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"za64rs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"za128rs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zaamo", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zabha", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zacas", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zalrsc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zawrs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zfbfmin", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zfa", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zfh", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zfhmin", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zfinx", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zdinx", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zqinx", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zhinx", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zhinxmin", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zbb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zba", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zbc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zbs", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zbkb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zbkc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zbkx", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zk", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zkn", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zknd", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zkne", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zknh", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zkr", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zks", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zksed", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zksh", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zkt", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zve32x", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zve32f", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zve64x", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zve64f", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zve64d", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zvbb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zvbc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zvfbfmin", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zvfbfwma", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zvfh", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zvfhmin", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zvkb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zvkg", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zvkn", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zvkng", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zvknc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zvkned", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zvknha", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zvknhb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zvksed", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zvksh", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zvks", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zvksg", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zvksc", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zvkt", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zvl32b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zvl64b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zvl128b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zvl256b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zvl512b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zvl1024b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zvl2048b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zvl4096b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zvl8192b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zvl16384b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zvl32768b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zvl65536b", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"ztso", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zca", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zcb", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zce", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zcf", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zcd", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zcmop", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zcmp", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zcmt", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"zclsd", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {NULL, 0, 0, 0, 0} }; @@ -1634,9 +1634,9 @@ {"xventanacondops", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xsfvcp", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xsfcease", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, - {"xsfvqmaccqoq", ISA_SPEC_CLASS_DRAFT, 1, 0, 0}, - {"xsfvqmaccdod", ISA_SPEC_CLASS_DRAFT, 1, 0, 0}, - {"xsfvfnrclipxfqf", ISA_SPEC_CLASS_DRAFT, 1, 0, 0}, + {"xsfvqmaccqoq", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"xsfvqmaccdod", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, + {"xsfvfnrclipxfqf", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xmipscbop", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xmipscmov", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 }, {"xmipsexectl", ISA_SPEC_CLASS_DRAFT, 1, 0, 0 },