RISC-V: Add missing disassembler option `max`
The flag already exists but it's not been exposed to user.
Signed-off-by: Marek Pikuła <m.pikula@partner.samsung.com>
diff --git a/binutils/doc/binutils.texi b/binutils/doc/binutils.texi
index b291670f..c74526e 100644
--- a/binutils/doc/binutils.texi
+++ b/binutils/doc/binutils.texi
@@ -2701,6 +2701,14 @@
For RISC-V, the following options are supported:
@table @code
+@item max
+Disassemble without checking architecture string. This is a best effort mode, so
+for overlapping ISA extensions the first match (possibly incorrect in a given
+context) will be used to decode the instruction. It's useful, if the ELF file
+doesn't expose ISA string, preventing automatic ISA subset deduction, and the
+default fallback ISA string (@code{rv64gc}) doesn't cover all instructions in
+the binary.
+
@item numeric
Print numeric register names, rather than ABI names (e.g., print @code{x2}
instead of @code{sp}).
diff --git a/opcodes/riscv-dis.c b/opcodes/riscv-dis.c
index f862ef2..277b8fd 100644
--- a/opcodes/riscv-dis.c
+++ b/opcodes/riscv-dis.c
@@ -69,7 +69,7 @@
const char (*riscv_fpr_names)[NRC];
/* If set, disassemble as most general instruction. */
bool no_aliases;
- /* If set, disassemble without checking architectire string, just like what
+ /* If set, disassemble without checking architecture string, just like what
we did at the beginning. */
bool all_ext;
};
@@ -83,6 +83,7 @@
pd->riscv_gpr_names = riscv_gpr_names_abi;
pd->riscv_fpr_names = riscv_fpr_names_abi;
pd->no_aliases = false;
+ pd->all_ext = false;
}
/* Parse RISC-V disassembler option (without arguments). */
@@ -1580,6 +1581,9 @@
riscv_option_arg_t arg;
} riscv_options[] =
{
+ { "max",
+ N_("Disassemble without checking architecture string."),
+ RISCV_OPTION_ARG_NONE },
{ "numeric",
N_("Print numeric register names, rather than ABI names."),
RISCV_OPTION_ARG_NONE },
