)]}'
{
  "commit": "888ff82e77d9ab8f04893a68cd6b4f518d6b50d9",
  "tree": "f5e7f51aec833bcd7a568c74bed591fec1db1184",
  "parents": [
    "84baa5fe937543578159de698cbb8c5f2e7a57c6"
  ],
  "author": {
    "name": "Maciej W. Rozycki",
    "email": "macro@redhat.com",
    "time": "Thu Jun 13 14:01:54 2024 +0100"
  },
  "committer": {
    "name": "Maciej W. Rozycki",
    "email": "macro@redhat.com",
    "time": "Thu Jun 13 14:01:54 2024 +0100"
  },
  "message": "MIPS/opcodes: Rework INSN_* flags into a consistent block\n\nFor historic reasons we have ended up with a random set of discontiguous\nbit assignments for INSN_* flags within `membership\u0027 and `exclusions\u0027\nmembers of `mips_opcode\u0027.  Some of the bits were previously used for ASE\nassignments and have been reused in a disorganised fashion since `ase\u0027\nhas been split off as a member on its own.  It makes them hard to track\nand maintain, and to see how many we still have available for future\nassignments.\n\nTherefore reorder the flags using consecutive bits and matching the\norder used with the switch statement in `cpu_is_member\u0027.\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "39c20a80123a3545f16c5fa81e49b96585db6ff1",
      "old_mode": 33188,
      "old_path": "include/opcode/mips.h",
      "new_id": "3ef74eb623a47e15eac8f2a761be1be77d780805",
      "new_mode": 33188,
      "new_path": "include/opcode/mips.h"
    }
  ]
}