)]}'
{
  "commit": "92f46037a0f672d1480f754f76a9bfa0334d099c",
  "tree": "4adfd6c80389f5dc1b0ae0f7f3834bf7836c45aa",
  "parents": [
    "4b177a76d5b759ba631568fb69e8750e99b43647"
  ],
  "author": {
    "name": "Tsukasa OI",
    "email": "research_trasio@irq.a4lg.com",
    "time": "Wed Aug 02 23:50:27 2023 +0000"
  },
  "committer": {
    "name": "Tsukasa OI",
    "email": "research_trasio@irq.a4lg.com",
    "time": "Thu Aug 03 00:01:31 2023 +0000"
  },
  "message": "RISC-V: Imply \u0027Zicsr\u0027 from \u0027Zve32x\u0027\n\nFurther clarification is made so that \u0027Zve32x\u0027 implies \u0027Zicsr\u0027 (the same\nimplication is already implemented in LLVM).\n\nSee related issue (the author raised) on the vector specification:\n\u003chttps://github.com/riscv/riscv-v-spec/issues/908\u003e\nand its resolution:\n\u003chttps://github.com/riscv/riscv-v-spec/issues/909\u003e\n\nbfd/ChangeLog:\n\n\t* elfxx-riscv.c (riscv_implicit_subsets): Add \u0027Zve32x\u0027 -\u003e \u0027Zicsr\u0027.\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "ba5165766b2b149bd82e065fec64d870ddc7a695",
      "old_mode": 33188,
      "old_path": "bfd/elfxx-riscv.c",
      "new_id": "2ce95d90df52005ff4390b5b1ada0043dbe0e352",
      "new_mode": 33188,
      "new_path": "bfd/elfxx-riscv.c"
    }
  ]
}