tree 4adfd6c80389f5dc1b0ae0f7f3834bf7836c45aa
parent 4b177a76d5b759ba631568fb69e8750e99b43647
author Tsukasa OI <research_trasio@irq.a4lg.com> 1691020227 +0000
committer Tsukasa OI <research_trasio@irq.a4lg.com> 1691020891 +0000

RISC-V: Imply 'Zicsr' from 'Zve32x'

Further clarification is made so that 'Zve32x' implies 'Zicsr' (the same
implication is already implemented in LLVM).

See related issue (the author raised) on the vector specification:
<https://github.com/riscv/riscv-v-spec/issues/908>
and its resolution:
<https://github.com/riscv/riscv-v-spec/issues/909>

bfd/ChangeLog:

	* elfxx-riscv.c (riscv_implicit_subsets): Add 'Zve32x' -> 'Zicsr'.