| commit | 99e1a184a791d30c09a86d6eca4528dc146c2c79 | [log] [tgz] |
|---|---|---|
| author | Andrew Burgess <andrew.burgess@embecosm.com> | Tue Dec 04 11:48:42 2018 +0000 |
| committer | Andrew Burgess <andrew.burgess@embecosm.com> | Tue Dec 11 11:36:52 2018 +0000 |
| tree | a93f9626946d8aec365af5b66891bc5dea60ae54 | |
| parent | 8970c0224e3c36c565672089e38de42765e87f47 [diff] |
gdb/riscv: Update test to handle targets without an fpu The FPU is optional on RISC-V. The gdb.base/float.exp test currently assumes that an fpu is always available on RISC-V. Update the test so that this is not the case. gdb/testsuite/ChangeLog: * gdb.base/float.exp: Handle RISC-V targets without an FPU.