| //Original:/proj/frio/dv/testcases/core/c_comp3op_pr_plus_pr_sh1/c_comp3op_pr_plus_pr_sh1.dsp | |
| // Spec Reference: comp3op pregs + pregs << 1 | |
| # mach: bfin | |
| .include "testutils.inc" | |
| start | |
| imm32 p1, 0x89ab1def; | |
| imm32 p2, 0x56781abc; | |
| imm32 p3, 0xdef01234; | |
| imm32 p4, 0x23451899; | |
| imm32 p5, 0x78911345; | |
| imm32 sp, 0x98761432; | |
| imm32 fp, 0x12341678; | |
| P1 = P1 + ( P1 << 1 ); | |
| P2 = P1 + ( P2 << 1 ); | |
| P3 = P1 + ( P3 << 1 ); | |
| P4 = P1 + ( P4 << 1 ); | |
| P5 = P1 + ( P5 << 1 ); | |
| SP = P1 + ( SP << 1 ); | |
| FP = P1 + FP; | |
| CHECKREG p1, 0x9D0159CD; | |
| CHECKREG p2, 0x49F18F45; | |
| CHECKREG p3, 0x5AE17E35; | |
| CHECKREG p4, 0xE38B8AFF; | |
| CHECKREG p5, 0x8E238057; | |
| CHECKREG sp, 0xCDED8231; | |
| CHECKREG fp, 0xAF357045; | |
| imm32 p1, 0x89abcd2f; | |
| imm32 p2, 0x56789a2c; | |
| imm32 p3, 0xdef01224; | |
| imm32 p4, 0x23456829; | |
| imm32 p5, 0x78912325; | |
| imm32 sp, 0x98765422; | |
| imm32 fp, 0x12345628; | |
| P1 = P2 + ( P1 << 1 ); | |
| P2 = P2 + ( P2 << 1 ); | |
| P3 = P2 + ( P3 << 1 ); | |
| P4 = P2 + ( P4 << 1 ); | |
| P5 = P2 + ( P5 << 1 ); | |
| SP = P2 + ( SP << 1 ); | |
| FP = P2 + ( FP << 1 ); | |
| CHECKREG p1, 0x69D0348A; | |
| CHECKREG p2, 0x0369CE84; | |
| CHECKREG p3, 0xC149F2CC; | |
| CHECKREG p4, 0x49F49ED6; | |
| CHECKREG p5, 0xF48C14CE; | |
| CHECKREG sp, 0x345676C8; | |
| CHECKREG fp, 0x27D27AD4; | |
| imm32 p1, 0x89abcde3; | |
| imm32 p2, 0x56789ab3; | |
| imm32 p3, 0xdef01233; | |
| imm32 p4, 0x23456893; | |
| imm32 p5, 0x78912343; | |
| imm32 sp, 0x98765433; | |
| imm32 fp, 0x12345673; | |
| P1 = P3 + ( P1 << 1 ); | |
| P2 = P3 + ( P2 << 1 ); | |
| P3 = P3 + ( P3 << 1 ); | |
| P4 = P3 + ( P4 << 1 ); | |
| P5 = P3 + ( P5 << 1 ); | |
| SP = P3 + ( SP << 1 ); | |
| FP = P3 + ( FP << 1 ); | |
| CHECKREG p1, 0xF247ADF9; | |
| CHECKREG p2, 0x8BE14799; | |
| CHECKREG p3, 0x9CD03699; | |
| CHECKREG p4, 0xE35B07BF; | |
| CHECKREG p5, 0x8DF27D1F; | |
| CHECKREG sp, 0xCDBCDEFF; | |
| CHECKREG fp, 0xC138E37F; | |
| imm32 p1, 0x49abcdef; | |
| imm32 p2, 0x46789abc; | |
| imm32 p3, 0x4ef01234; | |
| imm32 p4, 0x43456899; | |
| imm32 p5, 0x48912345; | |
| imm32 sp, 0x48765432; | |
| imm32 fp, 0x42345678; | |
| P1 = P4 + ( P1 << 1 ); | |
| P2 = P4 + ( P2 << 1 ); | |
| P3 = P4 + ( P3 << 1 ); | |
| P4 = P4 + ( P4 << 1 ); | |
| P5 = P4 + ( P5 << 1 ); | |
| SP = P4 + ( SP << 1 ); | |
| FP = P4 + ( FP << 1 ); | |
| CHECKREG p1, 0xD69D0477; | |
| CHECKREG p2, 0xD0369E11; | |
| CHECKREG p3, 0xE1258D01; | |
| CHECKREG p4, 0xC9D039CB; | |
| CHECKREG p5, 0x5AF28055; | |
| CHECKREG sp, 0x5ABCE22F; | |
| CHECKREG fp, 0x4E38E6BB; | |
| imm32 p1, 0x85abcdef; | |
| imm32 p2, 0x55789abc; | |
| imm32 p3, 0xd5f01234; | |
| imm32 p4, 0x25456899; | |
| imm32 p5, 0x75912345; | |
| imm32 sp, 0x95765432; | |
| imm32 fp, 0x15345678; | |
| P1 = P5 + ( P1 << 1 ); | |
| P2 = P5 + ( P2 << 1 ); | |
| P3 = P5 + ( P3 << 1 ); | |
| P4 = P5 + ( P4 << 1 ); | |
| P5 = P5 + ( P5 << 1 ); | |
| SP = P5 + ( SP << 1 ); | |
| FP = P5 + ( FP << 1 ); | |
| CHECKREG p1, 0x80E8BF23; | |
| CHECKREG p2, 0x208258BD; | |
| CHECKREG p3, 0x217147AD; | |
| CHECKREG p4, 0xC01BF477; | |
| CHECKREG p5, 0x60B369CF; | |
| CHECKREG sp, 0x8BA01233; | |
| CHECKREG fp, 0x8B1C16BF; | |
| imm32 p1, 0x89a6cdef; | |
| imm32 p2, 0x56769abc; | |
| imm32 p3, 0xdef61234; | |
| imm32 p4, 0x23466899; | |
| imm32 p5, 0x78962345; | |
| imm32 sp, 0x98765432; | |
| imm32 fp, 0x12365678; | |
| P1 = SP + ( P1 << 1 ); | |
| P2 = SP + ( P2 << 1 ); | |
| P3 = SP + ( P3 << 1 ); | |
| P4 = SP + ( P4 << 1 ); | |
| P5 = SP + ( P5 << 1 ); | |
| SP = SP + ( SP << 1 ); | |
| FP = SP + ( FP << 1 ); | |
| CHECKREG p1, 0xABC3F010; | |
| CHECKREG p2, 0x456389AA; | |
| CHECKREG p3, 0x5662789A; | |
| CHECKREG p4, 0xDF032564; | |
| CHECKREG p5, 0x89A29ABC; | |
| CHECKREG sp, 0xC962FC96; | |
| CHECKREG fp, 0xEDCFA986; | |
| imm32 p1, 0x89ab7def; | |
| imm32 p2, 0x56787abc; | |
| imm32 p3, 0xdef07234; | |
| imm32 p4, 0x23457899; | |
| imm32 p5, 0x78917345; | |
| imm32 sp, 0x98767432; | |
| imm32 fp, 0x12345678; | |
| P1 = FP + ( P1 << 1 ); | |
| P2 = FP + ( P2 << 1 ); | |
| P3 = FP + ( P3 << 1 ); | |
| P4 = FP + ( P4 << 1 ); | |
| P5 = FP + ( P5 << 1 ); | |
| SP = FP + ( SP << 1 ); | |
| FP = FP + ( FP << 1 ); | |
| CHECKREG p1, 0x258B5256; | |
| CHECKREG p2, 0xBF254BF0; | |
| CHECKREG p3, 0xD0153AE0; | |
| CHECKREG p4, 0x58BF47AA; | |
| CHECKREG p5, 0x03573D02; | |
| CHECKREG sp, 0x43213EDC; | |
| CHECKREG fp, 0x369D0368; | |
| imm32 p1, 0x29ab1def; | |
| imm32 p2, 0x52781abc; | |
| imm32 p3, 0xde201234; | |
| imm32 p4, 0x23421899; | |
| imm32 p5, 0x78912345; | |
| imm32 sp, 0x98761232; | |
| imm32 fp, 0x12341628; | |
| P1 = P3 + ( P1 << 1 ); | |
| P2 = P4 + ( P1 << 1 ); | |
| P3 = P5 + ( P1 << 1 ); | |
| P4 = SP + ( P1 << 1 ); | |
| P5 = FP + ( P1 << 1 ); | |
| FP = P1 + ( P1 << 1 ); | |
| CHECKREG p1, 0x31764E12; | |
| CHECKREG p2, 0x862EB4BD; | |
| CHECKREG p3, 0xDB7DBF69; | |
| CHECKREG p4, 0xFB62AE56; | |
| CHECKREG p5, 0x7520B24C; | |
| CHECKREG fp, 0x9462EA36; | |
| imm32 p1, 0x893bcd2f; | |
| imm32 p2, 0x56739a2c; | |
| imm32 p3, 0x3ef03224; | |
| imm32 p4, 0x23456329; | |
| imm32 p5, 0x78312335; | |
| imm32 sp, 0x98735423; | |
| imm32 fp, 0x12343628; | |
| P1 = P4 + ( P2 << 1 ); | |
| P2 = P5 + ( P2 << 1 ); | |
| P3 = SP + ( P2 << 1 ); | |
| P4 = FP + ( P2 << 1 ); | |
| SP = P1 + ( P2 << 1 ); | |
| FP = P2 + ( P2 << 1 ); | |
| CHECKREG p1, 0xD02C9781; | |
| CHECKREG p2, 0x2518578D; | |
| CHECKREG p3, 0xE2A4033D; | |
| CHECKREG p4, 0x5C64E542; | |
| CHECKREG sp, 0x1A5D469B; | |
| CHECKREG fp, 0x6F4906A7; | |
| imm32 p1, 0x894bcde3; | |
| imm32 p2, 0x56749ab3; | |
| imm32 p3, 0x4ef04233; | |
| imm32 p4, 0x24456493; | |
| imm32 p5, 0x78412344; | |
| imm32 sp, 0x98745434; | |
| imm32 fp, 0x12344673; | |
| P1 = P5 + ( P3 << 1 ); | |
| P2 = SP + ( P3 << 1 ); | |
| P3 = FP + ( P3 << 1 ); | |
| P5 = P1 + ( P3 << 1 ); | |
| SP = P2 + ( P3 << 1 ); | |
| FP = P3 + ( P3 << 1 ); | |
| CHECKREG p1, 0x1621A7AA; | |
| CHECKREG p2, 0x3654D89A; | |
| CHECKREG p3, 0xB014CAD9; | |
| CHECKREG p5, 0x764B3D5C; | |
| CHECKREG sp, 0x967E6E4C; | |
| CHECKREG fp, 0x103E608B; | |
| imm32 p1, 0x49abc5ef; | |
| imm32 p2, 0x46789a5c; | |
| imm32 p3, 0x4ef01235; | |
| imm32 p4, 0x53456899; | |
| imm32 p5, 0x45912345; | |
| imm32 sp, 0x48565432; | |
| imm32 fp, 0x42355678; | |
| P1 = SP + ( P4 << 1 ); | |
| P2 = FP + ( P4 << 1 ); | |
| P4 = P1 + ( P4 << 1 ); | |
| P5 = P2 + ( P4 << 1 ); | |
| SP = P3 + ( P4 << 1 ); | |
| FP = P4 + ( P4 << 1 ); | |
| CHECKREG p1, 0xEEE12564; | |
| CHECKREG p2, 0xE8C027AA; | |
| CHECKREG p4, 0x956BF696; | |
| CHECKREG p5, 0x139814D6; | |
| CHECKREG sp, 0x79C7FF61; | |
| CHECKREG fp, 0xC043E3C2; | |
| imm32 p1, 0x85ab6def; | |
| imm32 p2, 0x657896bc; | |
| imm32 p3, 0xd6f01264; | |
| imm32 p4, 0x25656896; | |
| imm32 p5, 0x75962345; | |
| imm32 sp, 0x95766432; | |
| imm32 fp, 0x15345678; | |
| P1 = FP + ( P5 << 1 ); | |
| P3 = P1 + ( P5 << 1 ); | |
| P4 = P2 + ( P5 << 1 ); | |
| P5 = P3 + ( P5 << 1 ); | |
| SP = P4 + ( P5 << 1 ); | |
| FP = P5 + ( P5 << 1 ); | |
| CHECKREG p1, 0x00609D02; | |
| CHECKREG p3, 0xEB8CE38C; | |
| CHECKREG p4, 0x50A4DD46; | |
| CHECKREG p5, 0xD6B92A16; | |
| CHECKREG sp, 0xFE173172; | |
| CHECKREG fp, 0x842B7E42; | |
| imm32 p1, 0x89a7cdef; | |
| imm32 p2, 0x56767abc; | |
| imm32 p3, 0xdef61734; | |
| imm32 p4, 0x73466879; | |
| imm32 p5, 0x77962347; | |
| imm32 sp, 0x98765432; | |
| imm32 fp, 0x12375678; | |
| P2 = P1 + ( SP << 1 ); | |
| P3 = P2 + ( SP << 1 ); | |
| P4 = P3 + ( SP << 1 ); | |
| P5 = P4 + ( SP << 1 ); | |
| SP = P5 + ( SP << 1 ); | |
| FP = SP + ( SP << 1 ); | |
| CHECKREG p2, 0xBA947653; | |
| CHECKREG p3, 0xEB811EB7; | |
| CHECKREG p4, 0x1C6DC71B; | |
| CHECKREG p5, 0x4D5A6F7F; | |
| CHECKREG sp, 0x7E4717E3; | |
| CHECKREG fp, 0x7AD547A9; | |
| imm32 p1, 0x88ab78ef; | |
| imm32 p2, 0x56887a8c; | |
| imm32 p3, 0x8ef87238; | |
| imm32 p4, 0x28458899; | |
| imm32 p5, 0x78817845; | |
| imm32 sp, 0x98787482; | |
| imm32 fp, 0x12348678; | |
| P1 = P2 + ( FP << 1 ); | |
| P2 = P3 + ( FP << 1 ); | |
| P3 = P4 + ( FP << 1 ); | |
| P4 = P5 + ( FP << 1 ); | |
| P5 = SP + ( FP << 1 ); | |
| SP = FP + ( FP << 1 ); | |
| CHECKREG p1, 0x7AF1877C; | |
| CHECKREG p2, 0xB3617F28; | |
| CHECKREG p3, 0x4CAE9589; | |
| CHECKREG p4, 0x9CEA8535; | |
| CHECKREG p5, 0xBCE18172; | |
| CHECKREG sp, 0x369D9368; | |
| pass |