| //Original:/proj/frio/dv/testcases/core/c_dsp32alu_rh_rnd12_m/c_dsp32alu_rh_rnd12_m.dsp | |
| // Spec Reference: dsp32alu dreg (half) | |
| # mach: bfin | |
| .include "testutils.inc" | |
| start | |
| imm32 r0, 0x45678ad1; | |
| imm32 r1, 0x2789ab1d; | |
| imm32 r2, 0xf4445545; | |
| imm32 r3, 0x46667767; | |
| imm32 r4, 0xe678891b; | |
| imm32 r5, 0x6f89ab1d; | |
| imm32 r6, 0x7444d565; | |
| imm32 r7, 0x8666b797; | |
| R0.H = R0 - R0 (RND12); | |
| R1.H = R0 - R1 (RND12); | |
| R2.H = R0 - R2 (RND12); | |
| R3.H = R0 - R3 (RND12); | |
| R4.H = R0 - R4 (RND12); | |
| R5.H = R0 - R5 (RND12); | |
| R6.H = R0 - R6 (RND12); | |
| R7.H = R0 - R7 (RND12); | |
| CHECKREG r0, 0x00008AD1; | |
| CHECKREG r1, 0x8000AB1D; | |
| CHECKREG r2, 0x7fff5545; | |
| CHECKREG r3, 0x80007767; | |
| CHECKREG r4, 0x7fff891B; | |
| CHECKREG r5, 0x8000AB1D; | |
| CHECKREG r6, 0x8000D565; | |
| CHECKREG r7, 0x7fffB797; | |
| imm32 r0, 0xd5678911; | |
| imm32 r1, 0x2789ab1d; | |
| imm32 r2, 0xa4445515; | |
| imm32 r3, 0x46667717; | |
| imm32 r4, 0x5b78891b; | |
| imm32 r5, 0x6789ab1d; | |
| imm32 r6, 0x74e45515; | |
| imm32 r7, 0x86a6b777; | |
| R0.H = R1 - R0 (RND12); | |
| R1.H = R1 - R1 (RND12); | |
| R2.H = R1 - R2 (RND12); | |
| R3.H = R1 - R3 (RND12); | |
| R4.H = R1 - R4 (RND12); | |
| R5.H = R1 - R5 (RND12); | |
| R6.H = R1 - R6 (RND12); | |
| R7.H = R1 - R7 (RND12); | |
| CHECKREG r0, 0x7fff8911; | |
| CHECKREG r1, 0x0000AB1D; | |
| CHECKREG r2, 0x7fff5515; | |
| CHECKREG r3, 0x80007717; | |
| CHECKREG r4, 0x8000891B; | |
| CHECKREG r5, 0x8000AB1D; | |
| CHECKREG r6, 0x80005515; | |
| CHECKREG r7, 0x7fffB777; | |
| imm32 r0, 0xa5678091; | |
| imm32 r1, 0x2789ab1d; | |
| imm32 r2, 0xb4445515; | |
| imm32 r3, 0x46667717; | |
| imm32 r4, 0xd678891b; | |
| imm32 r5, 0x6e89ab4d; | |
| imm32 r6, 0x74445567; | |
| imm32 r7, 0x86967757; | |
| R0.H = R2 - R0 (RND12); | |
| R1.H = R2 - R1 (RND12); | |
| R2.H = R2 - R2 (RND12); | |
| R3.H = R2 - R3 (RND12); | |
| R4.H = R2 - R4 (RND12); | |
| R5.H = R2 - R5 (RND12); | |
| R6.H = R2 - R6 (RND12); | |
| R7.H = R2 - R7 (RND12); | |
| CHECKREG r0, 0x7fff8091; | |
| CHECKREG r1, 0x8000AB1D; | |
| CHECKREG r2, 0x00005515; | |
| CHECKREG r3, 0x80007717; | |
| CHECKREG r4, 0x7fff891B; | |
| CHECKREG r5, 0x8000AB4D; | |
| CHECKREG r6, 0x80005567; | |
| CHECKREG r7, 0x7fff7757; | |
| imm32 r0, 0x35678991; | |
| imm32 r1, 0x2789ab8d; | |
| imm32 r2, 0xd4445515; | |
| imm32 r3, 0x46667737; | |
| imm32 r4, 0x5678891b; | |
| imm32 r5, 0xeab9ab4d; | |
| imm32 r6, 0x744e5515; | |
| imm32 r7, 0x866e747f; | |
| R0.H = R3 - R0 (RND12); | |
| R1.H = R3 - R1 (RND12); | |
| R2.H = R3 - R2 (RND12); | |
| R3.H = R3 - R3 (RND12); | |
| R4.H = R3 - R4 (RND12); | |
| R5.H = R3 - R5 (RND12); | |
| R6.H = R3 - R6 (RND12); | |
| R7.H = R3 - R7 (RND12); | |
| CHECKREG r0, 0x7fff8991; | |
| CHECKREG r1, 0x7fffAB8D; | |
| CHECKREG r2, 0x7fff5515; | |
| CHECKREG r3, 0x00007737; | |
| CHECKREG r4, 0x8000891B; | |
| CHECKREG r5, 0x7fffAB4D; | |
| CHECKREG r6, 0x80005515; | |
| CHECKREG r7, 0x7fff747F; | |
| imm32 r0, 0xe5678931; | |
| imm32 r1, 0x2789ab1d; | |
| imm32 r2, 0x34e45555; | |
| imm32 r3, 0xd6667767; | |
| imm32 r4, 0x5675891b; | |
| imm32 r5, 0x6789abfd; | |
| imm32 r6, 0xa4465515; | |
| imm32 r7, 0x8b66e7b7; | |
| R0.H = R4 - R0 (RND12); | |
| R1.H = R4 - R1 (RND12); | |
| R2.H = R4 - R2 (RND12); | |
| R3.H = R4 - R3 (RND12); | |
| R4.H = R4 - R4 (RND12); | |
| R5.H = R4 - R5 (RND12); | |
| R6.H = R4 - R6 (RND12); | |
| R7.H = R4 - R7 (RND12); | |
| CHECKREG r0, 0x7fff8931; | |
| CHECKREG r1, 0x7fffAB1D; | |
| CHECKREG r2, 0x7fff5555; | |
| CHECKREG r3, 0x7fff7767; | |
| CHECKREG r4, 0x0000891B; | |
| CHECKREG r5, 0x8000ABFD; | |
| CHECKREG r6, 0x7fff5515; | |
| CHECKREG r7, 0x7fffE7B7; | |
| imm32 r0, 0x35678931; | |
| imm32 r1, 0x2789ab4d; | |
| imm32 r2, 0x3e445585; | |
| imm32 r3, 0x46667717; | |
| imm32 r4, 0xe6f8899b; | |
| imm32 r5, 0x6789db1d; | |
| imm32 r6, 0xf44a5515; | |
| imm32 r7, 0x866b77b7; | |
| R0.H = R5 - R0 (RND12); | |
| R1.H = R5 - R1 (RND12); | |
| R2.H = R5 - R2 (RND12); | |
| R3.H = R5 - R3 (RND12); | |
| R4.H = R5 - R4 (RND12); | |
| R5.H = R5 - R5 (RND12); | |
| R6.H = R5 - R6 (RND12); | |
| R7.H = R5 - R7 (RND12); | |
| CHECKREG r0, 0x7fff8931; | |
| CHECKREG r1, 0x7fffAB4D; | |
| CHECKREG r2, 0x7fff5585; | |
| CHECKREG r3, 0x7fff7717; | |
| CHECKREG r4, 0x7fff899B; | |
| CHECKREG r5, 0x0000DB1D; | |
| CHECKREG r6, 0x7fff5515; | |
| CHECKREG r7, 0x7fff77B7; | |
| imm32 r0, 0xb5678911; | |
| imm32 r1, 0xc789ab1d; | |
| imm32 r2, 0x3ab45515; | |
| imm32 r3, 0x466b7717; | |
| imm32 r4, 0x4678e91b; | |
| imm32 r5, 0x6789af1d; | |
| imm32 r6, 0xf4445515; | |
| imm32 r7, 0x86e6f777; | |
| R0.H = R6 - R0 (RND12); | |
| R1.H = R6 - R1 (RND12); | |
| R2.H = R6 - R2 (RND12); | |
| R3.H = R6 - R3 (RND12); | |
| R4.H = R6 - R4 (RND12); | |
| R5.H = R6 - R5 (RND12); | |
| R6.H = R6 - R6 (RND12); | |
| R7.H = R6 - R7 (RND12); | |
| CHECKREG r0, 0x7fff8911; | |
| CHECKREG r1, 0x7fffAB1D; | |
| CHECKREG r2, 0x80005515; | |
| CHECKREG r3, 0x80007717; | |
| CHECKREG r4, 0x8000E91B; | |
| CHECKREG r5, 0x8000AF1D; | |
| CHECKREG r6, 0x00005515; | |
| CHECKREG r7, 0x7fffF777; | |
| imm32 r0, 0xab678051; | |
| imm32 r1, 0x2c89a26d; | |
| imm32 r2, 0x34d455f5; | |
| imm32 r3, 0x466e7717; | |
| imm32 r4, 0x567f89bb; | |
| imm32 r5, 0x6789ab1d; | |
| imm32 r6, 0x744e55a5; | |
| imm32 r7, 0x8666ab77; | |
| R0.H = R7 - R0 (RND12); | |
| R1.H = R7 - R1 (RND12); | |
| R2.H = R7 - R2 (RND12); | |
| R3.H = R7 - R3 (RND12); | |
| R4.H = R7 - R4 (RND12); | |
| R5.H = R7 - R5 (RND12); | |
| R6.H = R7 - R6 (RND12); | |
| R7.H = R7 - R7 (RND12); | |
| CHECKREG r0, 0x80008051; | |
| CHECKREG r1, 0x8000A26D; | |
| CHECKREG r2, 0x800055F5; | |
| CHECKREG r3, 0x80007717; | |
| CHECKREG r4, 0x800089BB; | |
| CHECKREG r5, 0x8000AB1D; | |
| CHECKREG r6, 0x800055A5; | |
| CHECKREG r7, 0x0000AB77; | |
| imm32 r0, 0x15678901; | |
| imm32 r1, 0x2789abad; | |
| imm32 r2, 0x34445515; | |
| imm32 r3, 0x466677d7; | |
| imm32 r4, 0x5678891b; | |
| imm32 r5, 0x6789ab1d; | |
| imm32 r6, 0x74445535; | |
| imm32 r7, 0x86667747; | |
| R6.H = R2 - R3 (RND12); | |
| R1.H = R4 - R5 (RND12); | |
| R5.H = R7 - R2 (RND12); | |
| R3.H = R0 - R0 (RND12); | |
| R0.H = R3 - R4 (RND12); | |
| R2.H = R5 - R7 (RND12); | |
| R7.H = R6 - R7 (RND12); | |
| R4.H = R1 - R6 (RND12); | |
| CHECKREG r0, 0x80008901; | |
| CHECKREG r1, 0x8000ABAD; | |
| CHECKREG r2, 0x99a35515; | |
| CHECKREG r3, 0x000077D7; | |
| CHECKREG r4, 0x0005891B; | |
| CHECKREG r5, 0x8000AB1D; | |
| CHECKREG r6, 0x80005535; | |
| CHECKREG r7, 0x999e7747; | |
| imm32 r0, 0x15678121; | |
| imm32 r1, 0x2789ab3d; | |
| imm32 r2, 0x34445565; | |
| imm32 r3, 0x4d667797; | |
| imm32 r4, 0x567889ab; | |
| imm32 r5, 0x67beabbd; | |
| imm32 r6, 0x7b445515; | |
| imm32 r7, 0x86d6e777; | |
| R3.H = R4 - R0 (RND12); | |
| R1.H = R6 - R3 (RND12); | |
| R4.H = R3 - R2 (RND12); | |
| R6.H = R7 - R1 (RND12); | |
| R2.H = R5 - R4 (RND12); | |
| R7.H = R2 - R7 (RND12); | |
| R0.H = R1 - R6 (RND12); | |
| R5.H = R0 - R5 (RND12); | |
| CHECKREG r0, 0x7fff8121; | |
| CHECKREG r1, 0xb44eAB3D; | |
| CHECKREG r2, 0x80005565; | |
| CHECKREG r3, 0x7fff7797; | |
| CHECKREG r4, 0x7fff89AB; | |
| CHECKREG r5, 0x7fffABBD; | |
| CHECKREG r6, 0x80005515; | |
| CHECKREG r7, 0x9297E777; | |
| pass |