blob: 0a2c43696d3c7f0fdb2c676921e9c2a94e520448 [file] [log] [blame]
# frv testcase for fbltlr $FCCi,$hint
# mach: all
.include "testutils.inc"
start
.global fbltlr
fbltlr:
set_spr_addr bad,lr
set_fcc 0x0 0
fbltlr fcc0,0
set_spr_addr bad,lr
set_fcc 0x1 1
fbltlr fcc1,1
set_spr_addr bad,lr
set_fcc 0x2 2
fbltlr fcc2,2
set_spr_addr bad,lr
set_fcc 0x3 3
fbltlr fcc3,3
set_spr_addr ok5,lr
set_fcc 0x4 0
fbltlr fcc0,0
fail
ok5:
set_spr_addr ok6,lr
set_fcc 0x5 1
fbltlr fcc1,1
fail
ok6:
set_spr_addr ok7,lr
set_fcc 0x6 2
fbltlr fcc2,2
fail
ok7:
set_spr_addr ok8,lr
set_fcc 0x7 3
fbltlr fcc3,3
fail
ok8:
set_spr_addr bad,lr
set_fcc 0x8 0
fbltlr fcc0,0
set_spr_addr bad,lr
set_fcc 0x9 1
fbltlr fcc1,1
set_spr_addr bad,lr
set_fcc 0xa 2
fbltlr fcc2,2
set_spr_addr bad,lr
set_fcc 0xb 3
fbltlr fcc3,3
set_spr_addr okd,lr
set_fcc 0xc 0
fbltlr fcc0,0
fail
okd:
set_spr_addr oke,lr
set_fcc 0xd 1
fbltlr fcc1,1
fail
oke:
set_spr_addr okf,lr
set_fcc 0xe 2
fbltlr fcc2,2
fail
okf:
set_spr_addr okg,lr
set_fcc 0xf 3
fbltlr fcc3,3
fail
okg:
pass
bad:
fail