blob: 4372e6c1adbbb47f4e7465a59b71e9b6a1489ac5 [file] [log] [blame]
# v850 sar
# mach: all
.include "testutils.inc"
# CY is set to 1 if the bit shifted out last is 1, else 0
# OV is set to zero.
# Z is set if the result is 0, else 0
noflags
seti 4, r1
seti 0x00000000, r2
sar r1, r2
flags z
reg r2, 0
noflags
seti 4, r1
seti 0x00000001, r2
sar r1, r2
flags z
reg r2, 0
noflags
seti 4, r1
seti 0x00000008, r2
sar r1, r2
flags c + z
reg r2, 0
noflags
seti 0x00000000, r2
sar 4, r2
flags z
reg r2, 0
noflags
seti 0x00000001, r2
sar 4, r2
flags z
reg r2, 0
noflags
seti 0x00000008, r2
sar 4, r2
flags c + z
reg r2, 0
# However, if the number of shifts is 0, CY is 0.
noflags
seti 0, r1
seti 0xffffffff, r2
sar r1, r2
flags s
reg r2, 0xffffffff
noflags
seti 0xffffffff, r2
sar 0, r2
flags s
reg r2, 0xffffffff
# Old MSB is copied as new MSB after shift
# S is 1 if the result is negative, else 0
noflags
seti 1, r1
seti 0x80000000, r2
sar r1, r2
flags s
reg r2, 0xc0000000
noflags
seti 1, r1
seti 0x40000000, r2
sar r1, r2
flags 0
reg r2, 0x20000000
pass