| commit | 3224e32fb84f034d190ad91d7b9ac86f6800d47a | [log] [tgz] |
|---|---|---|
| author | Jaydeep Patil <jaydeep.patil@imgtec.com> | Thu Feb 01 04:42:27 2024 +0000 |
| committer | Andrew Burgess <aburgess@redhat.com> | Tue Feb 13 11:04:04 2024 +0000 |
| tree | 239a301674c7c5040bda776596521d61b83b33ad | |
| parent | 4dad3c1e1c9e789addc0d196cef8e8ea22ddbeda [diff] |
sim: riscv: Add support for compressed integer instructions
Added support for simulation of compressed integer instruction set ("c").
Added test file sim/testsuite/riscv/c-ext.s to test compressed instructions.
The compressed instructions are available for models implementing C extension.
Such as RV32IC, RV64IC, RV32GC, RV64GC etc.
Approved-By: Andrew Burgess <aburgess@redhat.com>